Semiconductor device and electronic device

• US 7,742,351 B2
• Filed: 06/13/2007
• Issued: 06/22/2010
• Est. Priority Date: 06/30/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki, Ikeda, Takayuki, Inoue, Takayuki
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/762,146
• Publication Number:
  US 20080002454A1
• Time in Patent Office: 1,105 Days
• Field of Search: 365/203, 365/189.05, 365/189.07, 365/189.09, 365/189.11, 365/205, 365/230.06
• US Class Current: 365/203
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

In relation to reading of data in a memory, it is an object to provide a semiconductor device mounted with a low power consumption memory. A semiconductor device including a word line, a bit line, and a memory cell electrically connected to the word line and the bit line, further includes a precharge circuit for making the bit line have an electric potential for reading data stored in the memory cell. The precharge circuit is provided for each bit line and connected to the bit line. Further, the precharge circuit is capable of making each bit line have an electric potential for reading the data stored in the memory cell for each bit line.

Claims

1. A semiconductor device comprising:

a word line;

a first bit line and a second bit line;

a first memory cell electrically connected to the word line and the first bit line;

a second memory cell electrically connected to the word line and the second bit line;

a first switching element including a first terminal electrically connected to the first bit line;

a second switching element including a first terminal electrically connected to the second bit line;

a first precharge circuit configured to output a precharge potential to the first bit line, wherein the first precharge circuit is electrically connected to the first bit line through the first switching element;

a second precharge circuit configured to output a precharge potential to the second bit line, wherein the second precharge circuit is electrically connected to the second bit line through the second switching element; and

a circuit configured to operate the first switching element and the second switching element selectively.

2. A semiconductor device according to claim 1,

wherein the first precharge circuit includes a first transistor,

the second precharge circuit includes a second transistor,

one of a source and a drain of the first transistor is electrically connected to a second terminal of the first switching element, and

one of a source and a drain of the second transistor is electrically connected to a second terminal of the second switching element.

3. A semiconductor device according to claim 1,

wherein the first memory cell includes a first transistor,

the second memory cell includes a second transistor,

a gate of the first transistor is electrically connected to the word line, and one of a source and a drain of the first transistor is electrically connected to the first bit line, and

a gate of the second transistor is electrically connected to the word line, and one of a source and a drain of the second transistor is electrically connected to the second bit line.

4. A semiconductor device according to claim 2,

wherein the first transistor and the second transistor are both provided on a substrate, and wherein the substrate is any one of a glass substrate, a quartz substrate, and a plastic substrate.

5. A semiconductor device according to claim 2,

wherein the first transistor and the second transistor are formed on an SOI substrate.

6. A semiconductor device according to claim 1, wherein:

the first bit line is electrically connected to a first latch circuit configured to store an electric potential for reading data stored in the first memory cell; and

the second bit line is electrically connected to a second latch circuit configured to store an electric potential for reading data stored in the second memory cell.

7. An electronic device including a semiconductor device according to claim 1.

8. The semiconductor device of claim 1 wherein to operate the first switching element and the second switching element selectively, the circuit is configured to apply a signal to the first switching element without applying the signal to the second switching element.

9. The semiconductor device of claim 1 wherein to operate the first switching element and the second switching element selectively, the circuit is configured to concurrently apply a first signal to a third terminal of the first switching element and a second signal to a third terminal of the second switching element.

10. The semiconductor device of claim 1 wherein the first precharge circuit is configured to be operated with a read signal line electrically connected to a first terminal of the first precharge circuit, wherein the read signal line is not electrically connected to either the first or second switching elements.

11. A semiconductor device comprising:

a modulating circuit;

a demodulating circuit;

an antenna;

a logic circuit; and

a memory circuit including;

a word line,

a first bit line and a second bit line,

a first memory cell electrically connected to the word line and the first bit line,

a second memory cell electrically connected to the word line and the second bit line,

a first switching element including a first terminal electrically connected to the first bit line,

a second switching element including a first terminal electrically connected to the second bit line,

a first pre charge circuit configured to output a pre charge potential to the first bit line, wherein the first precharge circuit is electrically connected to the first bit line through the first switching element,

a second precharge circuit configured to output a precharge potential to the second bit line, wherein the second precharge circuit is electrically connected to the second bit line through the second switching element, and

a circuit configured to operate the first switching element and the second switching element selectively.

12. A semiconductor device according to claim 11, wherein:

the first precharge circuit includes a first transistor,

the second precharge circuit includes a second transistor,

one of a source and a drain of the first transistor is electrically connected to a second terminal of the first switching element, and

one of a source and a drain of the second transistor is electrically connected to a second terminal of the second switching element.

13. A semiconductor device according to claim 12,

wherein the first transistor and the second transistor are both provided on a substrate, and wherein the substrate is any one of a glass substrate, a quartz substrate, and a plastic substrate.

14. A semiconductor device according to claim 12,

wherein the first transistor and the second transistor are formed on an SOI substrate.

15. A semiconductor device according to claim 11,

wherein the first memory cell includes a first transistor,

the second memory cell includes a second transistor,

a gate of the first transistor is electrically connected to the word line, and one of a source and a drain of the first transistor is electrically connected to the first bit line, and

a gate of the second transistor is electrically connected to the word line, and one of a source and a drain of the second transistor is electrically connected to the second bit line.

16. A semiconductor device according to claim 11, wherein:

the first bit line is electrically connected to a first latch circuit configured to store an electric potential for reading data stored in the first memory cell; and

the second bit line is electrically connected to a second latch circuit configured to store an electric potential for reading data stored in the second memory cell.

17. An electronic device including a semiconductor device according to claim 11.

18. The semiconductor device of claim 11 wherein to operate the first switching element and the second switching element selectively, the circuit is configured to apply a signal to the first switching element without applying the signal to the second switching element.

19. The semiconductor device of claim 11 wherein to operate the first switching element and the second switching element selectively, the circuit is configured to concurrently apply a first signal to a third terminal of the first switching element and a second signal to a third terminal of the second switching element.

20. The semiconductor device of claim 11 wherein the first precharge circuit is configured to be operated with a read signal line electrically connected to a first terminal of the first precharge circuit, wherein the read signal line is not electrically connected to either the first or second switching elements.