Automatic IIP2 calibration architecture

• US 7,742,747 B2
• Filed: 01/25/2007
• Issued: 06/22/2010
• Est. Priority Date: 01/25/2007
• Status: Active Grant

• Current Assignee: Icera Canada ULC (NVIDIA Corporation)
• Original Assignee: Icera Canada ULC (NVIDIA Corporation)
• Inventors: Safiri, Hamid R., Manku, Tajinder, Bellaouar, Abdellatif, Holden, Alan
• Primary Examiner(s): Nguyen; Lee
• Application Number:
  US11/626,964
• Publication Number:
  US 20080182537A1
• Time in Patent Office: 1,244 Days
• Field of Search: 4551141-1142, 455/115.1, 455/226.1, 455295-296, 455/310, 455/317
• US Class Current: 455/114.1
• CPC Class Codes: H03D 2200/0045 Calibration of demodulators
• CPC Class Codes: H04B 1/12 Neutralising, balancing, or compensation arrangements
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements

Abstract

An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

Claims

1. A second order intermodulation product (IIP2) calibration system for a wireless device comprising:

a test signal generator including

a transmitter core circuit including an oscillator circuit for generating a base frequency signal, and

a test adaptor circuit for adding an offset signal corresponding to the second order tone to the base frequency signal, the test adaptor circuit generating the first RF signal in response to the base frequency signal;

a receiver path having an input node for receiving the first RF signal, circuits for down-converting the first RF signal into a base band signal based on a receive frequency, and signal processing circuits for generating a digital data signal corresponding to the base band signal, the circuits receiving a compensation signal for minimizing the second order tone; and

a calibration circuit for measuring said second order tone in said digital data signal and for generating the compensation signal.

2. The IIP2calibration system of claim 1, wherein the transmitter core circuit includes

a transmit clock generator circuit for generating the base frequency signal, and

a transmit path circuit for receiving one of a data signal and the offset signal, the transmit path circuit mixing the base frequency signal with the offset signal to generate the first RF signal.

3. The IIP2calibration system of claim 2, wherein the test adaptor circuit includes

a test signal generator for generating the offset signal, and

a switch circuit for selectively coupling the first RF signal to the input node.

4. The IIP2calibration system of claim 3, wherein the offset signal is a preset digital signal and the transmit path circuit includes

an analog to digital converter for converting the offset signal into an analog signal, and

a mixer circuit for mixing the base frequency signal with the offset signal to provide the first RF signal.

5. The IIP2calibration system of claim 1, wherein the test adaptor circuit includes

an offset generator for providing the offset signal,

a mixing circuit for mixing a replica base frequency signal with the offset signal to provide the first RF signal, and

a switch circuit for selectively coupling the first RF signal to the input node of the receiver path in a test mode of operation.

6. The IIP2calibration system of claim 5, wherein the offset generator includes

a test signal generator for providing a digital test signal, and

a digital to analog converter for receiving the digital test signal, and for converting the digital test signal into an analog signal corresponding to the offset signal.

7. The IIP2calibration system of claim 6, wherein the digital to analog converter is a component of a transmit path circuit.

8. A method for on-chip generation of an radio frequency (RF) test signal having a second order tone, comprising:

a) generating a base frequency signal from a native circuit;

b) generating an offset signal corresponding to the second order tone with a test circuit, the offset signal being a preset digital test signal;

c) converting the offset signal into an analog signal; and

,

d) mixing the base frequency signal with the offset signal to generate the RF test signal by a native transmit path circuit.

9. The method for on-chip generation of an RF test signal of claim 8, wherein the step of generating the base frequency includes enabling a receive clock generator circuit.

10. The method for on-chip generation of an RF test signal of claim 8, wherein the offset signal is an analog signal corresponding to a preset digital test signal.

11. The method for on-chip generation of an RF test signal of claim 10, including a step of converting the preset digital test signal into the analog signal.

12. The method for on-chip generation of an RF test signal of claim 8, wherein the step of generating the base frequency includes enabling a transmit clock generator circuit.

13. The method for on-chip generation of an RF test signal of claim 8, wherein a power amplifier of the native transmit path circuit is disabled while the RF test signal is generated.

14. A method for second order intermodulation (IIP2) testing and calibration of a wireless device, comprising:

a) detecting a calibration event;

b) generating a radio frequency (RF) test signal having a second order tone with native circuits of the wireless device by;

i) generating a base frequency signal by enabling a transmit clock generator circuit;

ii) generating a preset digital test signal corresponding to the second order tone with a test circuit;

iii) converting a preset digital test signal into an analog signal that corresponds to an offset signal; and

,

iv) mixing the base frequency signal with the offset signal by a native transmit path circuit to generate the RF test signal;

c) propagating the RF test signal through a receive path of the wireless device;

d) measuring a parameter of the second order tone and generating a corresponding compensation signal; and

e) adjusting one or more circuits of the receive path with the compensation signal for minimizing the second order tone.

15. The method of claim 14, wherein the step of detecting includes detecting one of a power up reset event, power on event and any preset enabling event.

16. The method of claim 14, wherein the step of propagating includes coupling the RF test signal to the receive path in response to the calibration event.

17. The method of claim 14, wherein the step of detecting includes decoupling an antenna from the receive path.

18. The method for on-chip generation of an RF test signal of claim 14, wherein a power amplifier of the native transmit path circuit is disabled while the RF test signal is generated.