Configurable IC with large carry chains

• US 7,743,085 B2
• Filed: 03/15/2005
• Issued: 06/22/2010
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Redgrave, Jason
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US11/082,222
• Publication Number:
  US 20070244960A1
• Time in Patent Office: 1,925 Days
• Field of Search: 708/230, 708/232, 708/710, 326/39
• US Class Current: 708/710
• CPC Class Codes: G06F 2207/3868 Bypass control, i.e. possibility to transfer an operand unchanged to the output
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components

Abstract

Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Claims

1. A configurable integrated circuit (“

IC”

) comprising;

a plurality of sets of circuits, each set of circuits for performing an addition or subtraction operation,

each set of circuits comprising (i) at least one circuit for producing a propagate signal and a generate signal and (ii) at least one carry circuit for producing a carry signal,

wherein the carry circuit of at least one set of circuits is arranged adjacent to the carry circuits of at least three other sets of circuits to reduce propagation delay of the carry signal from one set of circuits to another set of circuits.

2. The configurable IC of claim 1, wherein the plurality of sets of circuits includes N configurable logic circuits for producing propagate signals and generate signals for an N-bit add or subtract operation, wherein N is an integer value greater than two.

3. The configurable IC of claim 2, wherein each set of N configurable logic circuits is also for performing operations unrelated to add and subtract operations.

4. The configurable IC of claim 3, wherein to perform any operation, each configurable logic circuit receives a configuration data set that configures the logic circuit to perform the operation.

5. The configurable IC of claim 2, wherein the carry circuits for a set of N configurable logic circuits is one shared circuit that performs a carry chain operation for all N configurable logic circuits.

6. The configurable IC of claim 2, wherein the N configurable logic circuits are positioned next to each other in the configurable IC.

7. The configurable IC of claim 6, wherein the N configurable logic circuits also are placed around the carry circuits to increase the speed of the addition or subtraction operation.

8. The configurable IC of claim 2, wherein the carry circuit is a carry chain formed by serially connecting a set of one-bit carry circuits.

9. The configurable IC of claim 8, wherein the carry chain is a Manchester carry chain.

10. The configurable IC of claim 1, wherein the IC comprises at least 1000 configurable logic circuits and at least 250 carry circuits.

11. An electronic device comprising:

a configurable integrated circuit (“

IC”

) comprising;

a plurality of sets of circuits, each set of circuits for performing an addition or subtraction operation,

each set of circuits comprising (i) at least one circuit for producing a propagate signal and a generate signal and (ii) at least one carry circuit for producing a carry signal,

wherein the carry circuit of at least one set of circuits is arranged adjacent to the carry circuits of at least three other sets of circuits to reduce propagation delay of the carry signal from one set of circuits to another set of circuits.

12. The electronic device of claim 11, wherein the plurality of sets of circuits includes N configurable logic circuits for producing propagate signals and generate signals for an N-bit add or subtract operation, wherein N is an integer value greater than two.

13. The electronic device of claim 12, wherein the carry circuits for a set of N configurable logic circuits is one shared circuit that performs a carry chain operation for all N configurable logic circuits.

14. The electronic device of claim 12, wherein the N configurable logic circuits are positioned next to each other in the configurable IC, wherein the N configurable logic circuits also are placed around the carry circuit to increase the speed of the addition or subtraction operation.

15. The electronic device of claim 12, wherein the carry circuit is a carry chain formed by serially connecting a set of one-bit carry circuits.

16. The electronic device of claim 11, wherein the IC comprises at least 1000 configurable logic circuits and at least 250 carry circuits.

17. An integrated circuit (“

IC”

) comprising;

a) a first set of tiles aligned according to a first arrangement, each tile in the first set of tiles comprising a configurable logic circuit and a carry circuit, wherein the first arrangement orients each tile in the first set of tiles such that each of the carry circuits of the first set of tiles borders at least three other carry circuits in the first set of tiles; and

b) a second set of tiles aligned according to a second arrangement, each tile in the second set of tiles comprising a configurable logic circuit and a carry circuit, wherein the second arrangement orients each tile in the second set of tiles such that at least one of the carry circuits of the second set of tiles borders at least three other carry circuits in the second set of tiles,

wherein said first arrangement of configurable logic circuits and carry circuits performs a fast M-bit addition or subtraction operation and said second arrangement of configurable logic circuits and carry circuits performs a fast N-bit addition or subtraction operation, and

wherein an output of a carry circuit of the first set of tiles is supplied as an input to a carry circuit of the second set of tiles in order to perform an N+M-bit addition or subtraction operation.

18. The IC of claim 17, wherein the first set of tiles comprises at least four tiles and the second set of tiles comprises at least four tiles.

19. The IC of claim 17, wherein the first set of tiles is arranged in a row column alignment.

20. The IC of claim 19, wherein the row column alignment comprises positioning two tiles in each of two neighboring columns.

21. The IC of claim 20, wherein the row column alignment further comprises positioning each of the two tiles of each of the two neighboring columns in two neighboring rows.

22. The IC of claim 17, wherein M and N are equivalent integer values.

23. The IC of claim 17, wherein the configurable logic circuits of the first and second sets of tiles perform the addition or subtraction operation by producing propagate signals and generate signals based on a first set of inputs, a second set of inputs, and carry signals.