Serialization of data for communication with different-protocol slave in multi-chip bus implementation

• US 7,743,186 B2
• Filed: 04/27/2007
• Issued: 06/22/2010
• Est. Priority Date: 04/27/2007
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Bracamontes Del Toro, Rocendo
• Primary Examiner(s): Shin; Christopher B
• Application Number:
  US11/741,328
• Publication Number:
  US 20080270656A1
• Time in Patent Office: 1,152 Days
• Field of Search: 710 58- 61, 710305-315, 710105-110, 710 33- 35
• US Class Current: 710/58
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge.

Claims

1. A system comprising:

a bridge operative to interface a first bus that uses a first bus protocol to a bus matrix that uses a second bus protocol;

a first serializer coupled to the bridge, the first serializer operative to serialize information received from the bridge and send the serialized information over a communication bus;

a second serializer coupled to the communication bus, the second serializer operative to receive the serialized information and deserialize the serialized information; and

a slave using the first bus protocol and coupled to the second serializer, wherein the deserialized information is provided to the slave, and wherein the slave is operative to provide a response to the information from the bridge.

2. The system of claim 1 wherein the bridge and the first serializer are provided on a first device, and the second serializer and the slave are provided on a second device.

3. The system of claim 1 wherein each of the first and second serializers includes a mechanism operative to introduce automatic wait cycles in the bridge to allow the serialization of the information.

4. The system of claim 3 wherein the automatic wait cycles are inserted by the mechanism by setting a wait signal connected to the bridge, causing the bridge to wait during the serialization and deserialization.

5. The system of claim 3 wherein the mechanism includes a finite state machine, and wherein each of the first and second serializers includes one or more shift registers operative to serialize information to send over the communication bus and deserialize information received from a communication bus.

6. The system of claim 1 wherein the first bus protocol is Advanced Peripheral Bus (APB) and the second bus protocol is Advanced High Performance Bus (AHB).

7. The system of claim 1 wherein the first serializer includes a mechanism to resynchronize received serial information from a serial clock provided during serial transmission, to a clock governing the operation of the bridge.

8. The system of claim 1 wherein the second serializer includes a mechanism to resynchronize received serial information from a serial clock provided during serial transmission, to a clock governing the operation of the slave using the second bus protocol.

9. A method comprising:

receiving parallel bus information from a bridge, the parallel bus information addressed to a slave, wherein the bridge is operative to interface a first bus that uses a first bus protocol to a bus matrix that uses a second bus protocol different from the first protocol, and wherein the slave uses the first bus protocol;

serializing the parallel bus information and sending the serial information on a communication bus; and

inserting a wait cycle to the bridge during the serialization of the parallel bus information and sending of serial information.

10. The method of claim 9 wherein the parallel bus information from the bridge includes a read operation, and further comprising:

waiting for an indication that a response is being sent over the communication bus from the addressed slave; and

receiving and deserializing the response to provide the response to the bridge, wherein the wait cycle to the bridge extends until the response is ready to provide to the bridge.

11. The method of claim 9 wherein the receiving parallel bus information and inserting the wait cycle are performed by a finite state machine, and the serializing and deserializing of information is performed using one or more shift registers.

12. The method of claim 9 wherein the serial information is sent over the communication bus to the slave, the slave being provided on a device different from a device on which the bridge is provided.

13. The method of claim 9 wherein the received serial information from the communication bus is derived from information provided by the slave, the slave being provided on a device different from a device on which the bridge is provided.

14. The method of claim 9 further comprising resynchronizing the received serial information from a serial clock provided during serial transmission, to a clock governing the operation of the bus matrix.

15. The method of claim 9 wherein the first bus protocol is Advanced Peripheral Bus (APB) and the second bus protocol is Advanced High Performance Bus (AHB).

16. A method comprising:

serializing information using a first serializer to provide serialized information;

providing a select signal and an enable signal to a slave to enable communication with the slave that receives deserialized information from a second serializer, the select signal and enable signal provided by a bridge operative to interface bus components that use two different bus protocols in a bus system, wherein the second serializer deserializes the serialized information to provide the deserialized information to the slave; and

receiving a wait signal which causes a wait state in the bridge until serial communication with the slave has been completed.

17. The method of claim 16 wherein the wait signal is provided by the first serializer.

18. The method of claim 16 wherein the serial communication is provided over a communication bus to the slave, the bridge is provided on a first device, and the slave is provided on a second device.

19. The method of claim 18 wherein the first serializer provided on the first device and a response from the slave is serialized for communication back to the bridge.

20. The method of claim 16 wherein the two bus protocols include Advanced Peripheral Bus (APB) and Advanced High Performance Bus (AHB), and the slave uses the APB protocol.

21. A computer readable medium including program instructions to be implemented by a computer and for interfacing bus communications for a slave in a bus system, the program instructions for:

receiving parallel bus information from a bridge, the parallel bus information addressed to the slave, wherein the bridge is operative to interface a first bus that uses a first bus protocol to a bus matrix that uses a second bus protocol different from the first protocol, and wherein the slave uses the first bus protocol;

serializing the parallel bus information and sending the serial information on a communication bus; and

inserting a wait cycle to the bridge during the serialization of the parallel bus information and sending of serial information.

22. A computer readable medium including program instructions to be implemented by a computer and for interfacing bus communications for a slave, the program instructions for:

serializing information using a first serializer to provide serialized information;

providing a select signal and an enable signal to the slave to enable communication with the slave that receives deserialized information from a second serializer, the select signal and enable signal provided by a bridge operative to interface bus components that use two different bus protocols in a bus system, wherein the second serializer deserializes the serialized information to provide the deserialized information to the slave; and

receiving a wait signal which causes a wait state in the bridge until serial communication with the slave has been completed.