External memory controller node

• US 7,743,220 B2
• Filed: 05/06/2008
• Issued: 06/22/2010
• Est. Priority Date: 11/22/2002
• Status: Active Grant

• Current Assignee: Cornami, Inc.
• Original Assignee: QST Holdings LLC
• Inventors: Furtek, Frederick Curtis, Master, Paul L.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US12/115,843
• Publication Number:
  US 20080244197A1
• Time in Patent Office: 777 Days
• Field of Search: None
• US Class Current: 711/149
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H04L 67/60 Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources admission control or resource allocation H04L47/70

Abstract

A computing machine and system to provide multiple independent simultaneous memory requests is disclosed. The computing machine includes a memory. A plurality of heterogeneous computational nodes embodied in an integrated circuit are configured to make requests for memory accesses to the memory. A memory controller allows multiple independent simultaneous requests for memory accesses by the heterogeneous computational nodes to the memory.

Claims

1. A computing machine comprising:

a memory;

a plurality of heterogeneous computational nodes embodied in an integrated circuit and configured to make requests for memory accesses to the memory; and

a memory controller embodied in the integrated circuit that allows multiple independent simultaneous requests for memory accesses by the heterogeneous computational nodes to the memory.

2. The computing machine of claim 1, wherein the memory controller is configured to place the memory requests in a queue and allow accesses by the heterogeneous computational nodes to the memory in an order established by the queue.

3. The computing machine of claim 1, wherein the memory controller includes a predefined number of memory channels and is configured to receive memory requests assigned to corresponding memory channels of the predefined number of memory channels.

4. The computing machine of claim 2, wherein the memory controller is configured to allow accesses by the heterogeneous computational nodes to the memory over the assigned memory channels.

5. The computing machine of claim 3, wherein the memory controller is configured to allow requests sent over different channels of the plurality of memory channels to be processed in an order other than the order in which the requests are received by the memory controller.

6. The computing machine of claim 1, wherein the memory controller includes ports that have parameters, the memory controller configured to generate memory locations for the memory requests based on the parameters and to allow accesses by the heterogeneous computational nodes to the memory at the memory locations in response to the memory requests.

7. The computing machine circuit of claim 6, wherein the parameters configured by the memory controller in response to a peek or a poke.

8. The computing machine of claim 1, wherein the memory controller includes ports having parameters configured by the memory controller in response to the memory requests, the memory controller configured to allow accesses by the heterogeneous computational nodes to the memory using the configured parameters of the ports.

9. The computing machine of claim 8, wherein the parameters are configured by the memory controller in response to a peek or a poke.

10. The computing machine of claim 1, further comprising a programmable interconnection network providing programmable interconnections among the heterogeneous computational nodes and the memory controller routes the memory requests from the heterogeneous computational nodes to the memory controller, route data for the memory requests between the heterogeneous computational nodes and the memory via the memory controller, and route data between the heterogeneous computational nodes.

11. The computing machine of claim 1, wherein the adaptive computing device is in communication with an external memory device, and wherein the memory controller allows multiple independent simultaneous accesses by the heterogeneous computational nodes to the external memory device in response to requests for data transfer.

12. A computing machine embodied in an integrated circuit, the computing machine in communication with an external memory device, the integrated circuit comprising:

a plurality of heterogeneous computational nodes configured to make requests for data transfer to the external memory device; and

a controller that allows multiple independent simultaneous requests for data transfer by the heterogeneous computational nodes to the external memory device.

13. The computing machine of claim 12, wherein the controller is configured to place the requests for data transfer in a queue and allow accesses by the heterogeneous computational nodes to the external memory device in an order established by the queue.

14. The computing machine of claim 12, wherein the controller includes a predefined number of channels and is configured to receive requests for data-transfer, the requests assigned to corresponding channels of the predefined number of channels.

15. The computing machine of claim 14, wherein the controller is configured to allow accesses by the heterogeneous computational nodes to the external memory device over the assigned channels.

16. The computing machine of claim 14, wherein the controller is configured to allow requests sent over different channels of the plurality of channels to be processed in an order other than the order in which the requests are received by the controller.

17. The computing machine of claim 12, wherein the controller includes ports that have parameters.

18. The computing machine of claim 17 wherein the controller is configured to generate memory locations for the data transfer requests based on the parameters and is configured to allow accesses by the heterogeneous computing nodes to the external memory device at the memory locations in response to the data transfer requests.

19. The computing machine of claim 18, wherein the parameters are configured by the controller in response to a peek or a poke.

20. The computing machine of claim 12, wherein the controller includes ports that have parameters configured by the controller in response to the requests for data transfer, the controller configured to allow accesses by the heterogeneous computing nodes to the external memory device using the configured parameters of the ports.

21. The computing machine of claim 20, wherein the parameters are configured by the controller in response to a peek or a poke.

22. The computing machine of claim 12 further comprising a programmable interconnection network to provide programmable interconnections among the heterogeneous computational nodes and wherein the controller routes the data-transfer requests from the heterogeneous computational nodes to the controller, transfers data for the data-transfer requests between the heterogeneous computational nodes and the external memory device via the controller, and transfer data between the heterogeneous computational nodes.

23. An adaptive computing machine comprising:

a memory;

a plurality of heterogeneous computational nodes embodied in an integrated circuit and configured to make requests for memory accesses to the memory;

a programmable interconnection network embodied in the integrated circuit providing programmable interconnections among the heterogeneous computational nodes; and

a memory controller embodied in the integrated circuit that allows multiple independent simultaneous requests for memory accesses by the heterogeneous computational nodes to the memory in response to the memory requests.

24. The adaptive computing machine of claim 23, wherein the memory controller is configured to place the memory requests in a queue and allow accesses by the heterogeneous computational nodes to the memory in an order established by the queue.

25. The adaptive computing machine of claim 23, wherein the memory controller includes a predefined number of memory channels and is configured to receive memory requests assigned to corresponding memory channels of the predefined number of memory channels.

26. The adaptive computing machine of claim 25, wherein the memory controller is configured to allow accesses by the heterogeneous computational nodes to the memory over the assigned memory channels.

27. The adaptive computing machine of claim 25, wherein the memory controller is configured to allow requests sent over different channels of the plurality of memory channels to be processed in an order other than the order in which the requests are received by the memory controller.

28. The adaptive computing machine of claim 23, wherein the memory controller includes ports that have parameters, the memory controller configured to generate memory locations for the memory requests based on the parameters and to allow accesses by the heterogeneous computational nodes to the memory at the memory locations in response to the memory requests.

29. The adaptive computing machine of claim 28, wherein the parameters configured by the memory controller in response to a peek or a poke.

30. The adaptive computing machine of claim 23, wherein the memory controller includes ports having parameters configured by the memory controller in response to the memory requests, the memory controller configured to allow accesses by the heterogeneous computational nodes to the memory using the configured parameters of the ports.

31. The adaptive computing machine of claim 30, wherein the parameters are configured by the memory controller in response to a peek or a poke.

32. The adaptive computing machine of claim 23, wherein the memory controller routes the memory requests from the heterogeneous computational nodes to the memory controller, route data for the memory requests between the heterogeneous computational nodes and the memory via the memory controller, and route data between the heterogeneous computational nodes.

33. The adaptive computing machine of claim 23, wherein the adaptive computing device is in communication with an external memory device, and wherein the memory controller allows multiple independent simultaneous accesses by the heterogeneous computational nodes to the external memory device in response to requests for data transfer.

34. An adaptive computing machine embodied in an integrated circuit and in communication with an external memory device, the adaptive computing machine comprising:

a plurality of heterogeneous computational nodes configured to make memory requests for data transfer to the external memory device;

a programmable interconnection network to provide programmable interconnections among the heterogeneous computational nodes; and

a controller that allows multiple independent simultaneous requests for data transfer by the heterogeneous computational nodes to the external memory device.

35. The adaptive computing machine of claim 34, wherein the controller is configured to place the requests for data transfer in a queue and allow accesses by the heterogeneous computational nodes to the external memory device in an order established by the queue.

36. The adaptive computing machine of claim 34, wherein the controller includes a predefined number of channels and is configured to receive requests for data-transfer, the requests assigned to corresponding channels of the predefined number of channels.

37. The adaptive computing machine of claim 36, wherein the controller is configured to allow accesses by the heterogeneous computational nodes to the external device with memory over the assigned channels.

38. The adaptive computing machine of claim 36, wherein the controller is configured to allow requests sent over different channels of the plurality of channels to be processed in an order other than the order in which the requests are received by the controller.

39. The adaptive computing machine of claim 34, wherein the controller includes ports that have parameters.

40. The adaptive computing machine of claim 39 wherein the controller is configured to generate memory locations for the data transfer requests based on the parameters and is configured to allow accesses by the heterogeneous computing nodes to the external memory device at the memory locations in response to the data transfer requests.

41. The adaptive computing machine of claim 40, wherein the parameters are configured by the controller in response to a peek or a poke.

42. The adaptive computing machine of claim 34, wherein the controller includes ports that have parameters configured by the controller in response to the requests for data transfer, the controller configured to allow accesses by the heterogeneous computing nodes to the external memory device using the configured parameters of the ports.

43. The adaptive computing machine of claim 42, wherein the parameters are configured by the controller in response to a peek or a poke.

44. The adaptive computing machine of claim 42, wherein the controller routes the data-transfer requests from the heterogeneous computational nodes to the controller, transfers data for the data-transfer requests between the heterogeneous computational nodes and the external memory device via the controller, and transfer data between the heterogeneous computational nodes.