Memory array programming circuit and a method for using the circuit
First Claim
1. A method of programming a multi-level cell (MLC) memory array comprising deriving a programming vector associated with at least one specific program state, wherein the programming vector is derived by mapping a first pair of bits from a binary input register to a first element in the programming vector.
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Accused Products
Abstract
A multi-level cell (MLC) memory array may be programmed using a programming circuit having a binary input register to store data to be input into the MLC array and a register to store a programming vector, where each element in the programming vector corresponds to a charge storage region of an MLC in the array. A controller may map pairs of bits from the input register to elements in the programming vector, such that mapping a pair of bits to an element of the programming vector may set the vector element to a “program” value if the pair of bits corresponds to at least one specific program state associated with the programming vector.
610 Citations
35 Claims
- 1. A method of programming a multi-level cell (MLC) memory array comprising deriving a programming vector associated with at least one specific program state, wherein the programming vector is derived by mapping a first pair of bits from a binary input register to a first element in the programming vector.
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9. A method of programming a multi-level cell (MLC) memory array comprising:
- deriving at least one programming vector associated with at least two specific program states, and concurrently programming a set of cells, wherein at least two cells in the set of cells are designated for programming to different threshold voltages corresponding to the at least two specific program states.
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10. A multi-level cell (“
- MLC”
) memory array programming circuit comprising;
a controller adapted to map a first pair of bits from an input register to a first element of a programming vector associated with at least one specific program state. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
- MLC”
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23. A multi-level cell (“
- MLC”
) memory device comprising a non-volatile memory array; and
a controller adapted to map a first pair of bits from an input register to a first element of a programming vector associated with at least one specific program state. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
- MLC”
Specification