Integrated circuit incorporating protection from power supply attacks

• US 7,743,262 B2
• Filed: 06/14/2004
• Issued: 06/22/2010
• Est. Priority Date: 07/15/1997
• Status: Expired due to Fees

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Walmsley, Simon Robert
• Primary Examiner(s): Truong; Thanhnga B
• Application Number:
  US10/866,608
• Publication Number:
  US 20040236961A1
• Time in Patent Office: 2,199 Days
• Field of Search: 713/194, 713/340, 713/320, 713/300, 713/172, 726/36, 340/429, 340/566, 361/1, 235/375, 235/379, 235/380, 307/43, 327/63, 327/78, 327/142, 327/143, 327/198, 327/162, 365/222, 323/268
• US Class Current: 713/194
• CPC Class Codes: B41J 2/16585 for paper-width or non-reciprocating print heads
• CPC Class Codes: B41J 2/17503 Ink cartridges
• CPC Class Codes: B41J 2/17513 Inner structure
• CPC Class Codes: B41J 2/17596 Ink pumps, ink valves
• CPC Class Codes: G06K 1/121 by printing code marks applying code marks to labels B65C9/46; marking or coding completed packages B65B61/26
• CPC Class Codes: G06K 19/06037 multi-dimensional coding
• CPC Class Codes: G06K 7/14 using light without selection of wavelength, e.g. sensing reflected white light G06K7/10831 - G06K7/1097 take precedence
• CPC Class Codes: G06K 7/1417 2D bar codes
• CPC Class Codes: G07F 7/08 by coded identity card or credit card or other personal identification means without personal verification means G07F7/02
• CPC Class Codes: G07F 7/086 by passive credit-cards adapted therefor, e.g. constructive particularities to avoid counterfeiting, e.g. by inclusion of a physical or chemical security-layer for security documents G07D7/00; for the reading of record-carriers in general G06K7/00; for the design of coded credit-cards G06K19/10
• CPC Class Codes: G07F 7/12 Card verification
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: H04N 23/00 Cameras or camera modules comprising electronic image sensors; Control thereof
• CPC Class Codes: H04N 5/2628 Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

An integrated circuit including: non-volatile memory for containing secret information; and a detection unit for preventing at least one form of power supply attack on the secret information, the detection unit comprising:

• • a first comparator having a first input connected to a first reference voltage and a second input connected to a power supply line, the first comparator being configured to output a first detection signal when a power supply voltage moves beyond a first predetermined limit determined by the first reference voltage; and
  • an output to provide a signal to delete, overwrite, or otherwise render unreadable at least the secret information in the memory when the first detection signal is output by the first comparator.

Claims

1. An integrated circuit including:

non-volatile memory for storing secret information and an indicator that the secret information is stored therein; and

a detection unit for preventing at least one form of power supply attack on the secret information, the detection unit comprising;

a comparator having a first input connected to a reference voltage and a second input connected to a power supply line, the comparator being configured to output a detection signal when a power supply voltage is under a predetermined limit determined by the reference voltage; and

an output connected into a reset line of the integrated circuit, the output providing a reset signal to first delete, overwrite, or otherwise render unreadable the indicator and then delete, overwrite, or otherwise render unreadable the secret information in the memory when the detection signal is output by the comparator,

wherein the reset signal is provided when the power supply voltage drops below the predetermined limit due to a power-down of the integrated circuit.

2. An integrated circuit according to claim 1, wherein the reset line is a tamper detection line, the tamper detection line responding to the signal to delete, overwrite, or otherwise render unreadable at least the secret information in the memory.

3. An integrated circuit according to claim 1, wherein the detection unit is implemented in CMOS.

4. An integrated circuit according to claim 1, wherein the detection unit is covered by a tamper detection line, or by a tamper prevention line, or both.