Optimizing integrated circuit design through use of sequential timing information

• US 7,743,354 B2
• Filed: 05/02/2007
• Issued: 06/22/2010
• Est. Priority Date: 05/02/2007
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Chong, Philip, Sentovich, Ellen, Kuehlmann, Andreas, Passerone, Roberto, Albrecht, Christoph
• Primary Examiner(s): Do; Thuan
• Application Number:
  US11/743,301
• Publication Number:
  US 20080276208A1
• Time in Patent Office: 1,147 Days
• Field of Search: 716/2, 716/6, 716/17
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.

Claims

1. A method to determine a measure of sequential flexibility in a circuit design comprising:

obtaining a value for a limit upon clock cycle duration; and

using a computer to determine for a register in the circuit design, a limit upon addition of delay that can be added to a structural cycle in which the register is a constituent, which is not greater than any of respective maximal delays that can be added to respective structural cycles in which the register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

2. The method of claim 1 further including:

identifying a structural cycle in the design that has a selected proportionality of delay to number of registers;

wherein obtaining includes determining a value for a limit upon clock cycle duration that is at least sufficient to propagate a signal about the identified structural cycle.

3. The method of claim 2, wherein identifying a structural cycle includes identifying a critical cycle.

4. The method of claim 1 further including:

identifying a critical cycle in the design;

wherein obtaining includes determining a minimal clock cycle duration sufficient to propagate a signal about the identified structural cycle without incurring a setup time violation.

5. The method of claim 1, wherein determining a limit upon addition of delay for the register in the circuit design includes identifying a minimum delay from among the respective maximal delays.

6. The method of claim 1, further including:

determining a limit upon addition of delay includes determining respective maximal limits of additional delay of individual structural cycles in which the register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

7. The method of claim 6, wherein determining a limit upon addition of delay includes determining a limit that is not greater than each individual maximal limit of additional delay of individual structural cycles in which the register is a constituent.

8. The method of claim 6, wherein determining a limit upon addition of delay includes determining a limit that is substantially equal to a minimal addition of delay selected from among respective maximal limits of addition of delay of individual respective structural cycles in which the register is a constituent.

9. The method of claim 1, wherein obtaining a limit upon clock cycle duration includes:

determining a proportionality of delay in at least one selected structural cycle in the design to number of registers in the at least one selected structural cycle.

10. The method of claim 1, wherein obtaining a limit upon clock cycle duration includes:

determining a proportionality of delay in at least one selected structural cycle in the design to number of registers in the at least one selected structural cycle; and

selecting a value for the limit upon clock cycle duration that is at least sufficient to propagate a signal about the at least one selected structural cycle.

11. The method of claim 1, wherein obtaining a limit upon clock cycle duration includes:

identifying in the circuit design a structural cycle having a largest proportionality of delay to number of registers; and

selecting a value for the limit upon clock cycle duration that is at least sufficient to propagate a signal about the identified structural cycle.

12. The method of claim 1, wherein obtaining a limit upon clock cycle duration includes:

identifying in the circuit design a structural cycle having a largest proportionality of delay to number of registers; and

selecting a value for the limit upon clock cycle duration that substantially equal to proportionality of delay in the identified structural cycle to number of registers in the identified structural cycle.

13. The method of claim 1 further including:

determining for each of multiple respective registers in the circuit design, respective compatible limits upon addition of delay, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

14. The method of claim 1 further including:

determining for each of multiple respective registers, a respective limit upon addition of delay that is not greater than each individual maximal limit of delay for each individual structural cycle in which such respective register is a constituent, based upon the clock cycle duration that is not greater than the obtained limit upon clock cycle duration;

determining compatible limits upon structural cycle delay for the multiple respective registers, based upon the respective determined limits upon addition of delay and based upon the clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

15. The method of claim 1 further including:

determining for each of multiple respective registers, a respective limit upon addition of delay that is substantially equal to a minimal limit upon addition of delay from among maximal limits of addition of delay for each structural cycle in which such respective register is a constituent, based upon the clock cycle duration that is not greater than the obtained limit upon clock cycle duration; and

determining compatible limits upon delay for the multiple respective registers, based upon the respective determined limits upon addition of delay and based upon the clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

16. The method of claim 1 further including:

determining for each of multiple respective registers in the circuit design, respective balanced compatible maximal limits upon addition of delay, based upon the clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

17. The method of claim 1, wherein obtaining a limit upon clock cycle duration includes:

determining a proportionality of delay in at least one structural cycle in the design to number of registers in the at least one structural cycle; and

a value for the limit upon clock cycle duration that is at least sufficient to propagate a signal about the at least one structural cycle; and

further including;

selecting a delay that is not greater than any of respective maximal delays that can be added to one or more respective structural cycles in which the at least one register is a constituent, based upon the clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

18. The method of claim 1, wherein obtaining a limit upon clock cycle duration includes:

identifying in the circuit design a structural cycle having a largest proportionality of delay to number of registers; and

selecting a value for the limit upon clock cycle duration that is at least sufficient to propagate a signal about the identified structural cycle; and

further including;

identifying a minimum delay from among respective maximal delays that can be added to respective structural cycles in which the at least one register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

19. The method of claim 1, further including:

determining for each of multiple respective registers in the circuit design, a respective limit upon addition of delay that is not greater than each individual maximal limit of delay for each individual structural cycle in which such respective register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration; and

providing a visual representation of the circuit design; and

annotating the visual representation to indicate determined limits upon addition of delay for at least one register shown in the visual representation.

20. The method of claim 19 further including:

determining combinational slack of multiple paths in the circuit design; and

annotating the visual representation to indicate determined combinational slack of multiple paths shown in the visual representation.

21. The method of claim 19, wherein the visual representation includes RTL code.

22. The method of claim 19, wherein the visual representation includes a schematic diagram.

23. The method of claim 19, wherein obtaining a limit upon clock cycle duration applicable to the circuit design includes:

identifying a structural cycle having a largest proportionality of delay to number of registers; and

selecting a value that is substantially equal to the proportionality of delay to number of registers in the identified structural cycle.

24. A method to determine a measure of sequential flexibility in a circuit design comprising:

determining a limit upon clock cycle duration indicative of a highest proportion of delay to number of registers from among a plurality of structural cycles in the design; and

using a computer to determine for a register in the circuit design, a maximal limit upon addition of delay that can be added to a structural cycle in which the register is a constituent, wherein the maximal limit is substantially equal to a minimal addition of delay selected from among maximal limits of additional delay that can be added to individual structural cycles in which the circuit element is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

25. A method to determine a measure of sequential flexibility in a circuit design comprising:

determining a minimum clock cycle that can be used to propagate a signal about critical cycle in a circuit design;

wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; and

using a computer to determine for a register in the circuit design, sequential slack associated with the circuit element;

wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the register is a constituent, based upon the determined limit upon clock cycle duration.

26. A system to determine a measure of sequential flexibility in a circuit design comprising:

means for obtaining a value for a limit upon clock cycle duration; and

means for determining for a register in the circuit design, a limit upon addition of delay that can be added to a structural cycle in which the register is a constituent, which is not greater than any of respective maximal delays that can be added to respective structural cycles in which the register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

27. The method of claim 26 further including:

identifying a structural cycle in the design that has a selected proportionality of delay to number of registers;

wherein obtaining includes determining a value for a limit upon clock cycle duration that is at least sufficient to propagate a signal about the identified structural cycle.

28. The method of claim 27, wherein identifying a structural cycle includes identifying a critical cycle.

29. The method of claim 26 further including:

identifying a critical cycle in the design;

wherein obtaining includes determining a minimal clock cycle duration sufficient to propagate a signal about the identified structural cycle without incurring a setup time violation.

30. An article of manufacture that includes a computer data storage device, encoded with code structure, when executed by a computer causes the computer data storage device to implement a method, comprising:

obtaining a value for a limit upon clock cycle duration; and

using a computer to determine for a register in the circuit design, a limit upon addition of delay that can be added to a structural cycle in which the register is a constituent, which is not greater than any of respective maximal delays that can be added to respective structural cycles in which the register is a constituent, based upon a clock cycle duration that is not greater than the obtained limit upon clock cycle duration.

31. The method of claim 30 further including:

identifying a structural cycle in the design that has a selected proportionality of delay to number of registers;

wherein obtaining includes determining a value for a limit upon clock cycle duration that is at least sufficient to propagate a signal about the identified structural cycle.

32. The method of claim 31, wherein identifying a structural cycle includes identifying a critical cycle.

33. The method of claim 30 further including:

identifying a critical cycle in the design;

wherein obtaining includes determining a minimal clock cycle duration sufficient to propagate a signal about the identified structural cycle without incurring a setup time violation.