Semiconductor device and memory card having the same
First Claim
1. A memory system applicable to a memory device having a controller which includes a plurality of connection portions and a circuit operable in accordance with an internal clock, the memory system including:
- an interface unit configured to notify an external apparatus of information without using the circuit upon receiving a predetermined command from the external apparatus before the memory device enters a standby state,wherein the information is determined depending on whether each of the plurality of connection portions is electrically connected to a power terminal or a ground terminal.
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Accused Products
Abstract
A semiconductor device includes a first circuit which operates in accordance with an internal clock, a second circuit which generates information of which an external apparatus is to be notified, an interface section which notifies the external apparatus of the information generated by the second circuit without using the first circuit upon receiving a predetermined command from the external apparatus, and a plurality of terminals each of which is connectable to one of power terminals and ground terminals provided on a substrate. The information is determined depending on whether each of the plurality of terminals is electrically connected to the power terminal or ground terminal on the substrate.
8 Citations
8 Claims
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1. A memory system applicable to a memory device having a controller which includes a plurality of connection portions and a circuit operable in accordance with an internal clock, the memory system including:
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an interface unit configured to notify an external apparatus of information without using the circuit upon receiving a predetermined command from the external apparatus before the memory device enters a standby state, wherein the information is determined depending on whether each of the plurality of connection portions is electrically connected to a power terminal or a ground terminal. - View Dependent Claims (2, 3)
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4. A memory system applicable to a memory device having a controller which includes a plurality of connection portions and a circuit operable in accordance with an internal clock, the memory system including:
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an interface unit configured to notify an external apparatus of information without using the circuit upon receiving a predetermined command from the external apparatus before the memory device enters a standby state, wherein the information is determined depending on whether or not each of the plurality of connection portions is electrically connected to one of a plurality of terminals. - View Dependent Claims (5, 6, 7, 8)
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Specification