Pin substrate and package

• US 7,745,244 B2
• Filed: 06/23/2008
• Issued: 06/29/2010
• Est. Priority Date: 06/23/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yuan, Zhongfa, Liu, Yong, Qian, Qiuxiao, Liu, Yumin
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): Payen; Marvin
• Application Number:
  US12/144,289
• Publication Number:
  US 20090315171A1
• Time in Patent Office: 736 Days
• Field of Search: 438/25, 438/26, 438/33, 438/55, 438/58, 438/64, 438/143
• US Class Current: 438/33
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 2201/10287 : Metal wires as connectors or conductors
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: H05K 2203/0235 : Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/4038 : Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: Y10T 29/49158 : with molding of insulated base

Abstract

A semiconductor die package. Embodiments of the package can include a substrate with solid conductive pins disposed throughout. A semiconductor die can be attached to a surface of the substrate. Electrical connection to the semiconductor die can be provided by the solid conductive pins.

Claims

1. A method of forming a substrate for use in a semiconductor package, the method comprising:

inserting a plurality of conductive wires into an alignment fixture;

placing at least a portion of the plurality of conductive wires and at least a portion of the alignment fixture in a mold, wherein the mold is separate from the alignment fixture;

filling the mold with a molding compound;

curing the molding compound to create a pre-substrate block; and

cutting the pre-substrate block, wherein cutting the pre-substrate block comprises cutting the plurality of conductive wires.

2. The method of claim 1 wherein the mold is in the shape of a square cylinder.

3. The method of claim 1 wherein the mold is in the shape of a round cylinder.

4. The method of claim 1 wherein the molding compound comprises an epoxy molding compound.

5. The method of claim 1 wherein each wire in the plurality of conductive wires includes a first end surface and a second end surface, and the molding compound comprises a first and second surface after cutting the pre-substrate block, further wherein the second surface of the molding compound is substantially co-planar with the second end surface of each wire in the plurality of conductive wires, and the first surface of the molding compound is substantially co-planar with the first end surface of each wire in the plurality of conductive wires.

6. The method of claim 1 wherein each wire in the plurality of conductive wires comprises copper.

7. The method of claim 1 wherein each wire in the plurality of conductive wires comprises gold.

8. The method of claim 6, wherein each wire in the plurality of conductive wires comprises a solid conducting material.

9. The method of claim 7, wherein each wire in the plurality of conductive wires comprises a solid conducting material.

10. The method of claim 1, wherein the alignment fixture includes a top plate having holes and a bottom plate having holes.

12. The method of claim 10, wherein the placing the at least a portion of the plurality of conductive wires within the alignment fixture comprises:

inserting top portions of the plurality of conductive wires into the holes in the top plate;

inserting bottom portions of the plurality of conductive wires into the holes in the bottom plate;

melting the bottom portions of the plurality of conductive wires to form flash balls; and

moving the top plate and the bottom plate outward.

13. The method of claim 10, wherein the top plate has a top plate inner side, and the bottom plate has a bottom plate inner side, further wherein both the top plate inner side and the bottom plate inner side are coated with a release layer.

14. The method of claim 12, wherein the top plate and the bottom plate are slidably coupled to one or more guides.

15. The method of claim 14, wherein the top plate is a first top plate, the method further comprising:

bending the top portions of the plurality of conductive wires;

attaching a second top plate to the one or more guides;

moving the second top plate inwards to clamp the bent top portions of the plurality of conductive wires against the first top plate.

11. A method of forming a substrate for use in a semiconductor package, the method comprising:

placing a plurality of conductive wires in a mold, wherein the placing a plurality of conductive wires in a mold includes placing the plurality of conductive wires within an alignment fixture, wherein the alignment fixture includes a top plate having holes and a bottom plate having holes, wherein the mold includes a slot, the method further comprising putting the top plate within the slot;

filling the mold with a molding compound;

curing the molding compound to create a pre-substrate block; and

cutting the pre-substrate block.