Fabrication of capacitive micromachined ultrasonic transducers by local oxidation

• US 7,745,248 B2
• Filed: 10/14/2008
• Issued: 06/29/2010
• Est. Priority Date: 10/18/2007
• Status: Active Grant

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Park, Kwan Kyu, Khuri-Yakub, Butrus T., Kupnik, Mario
• Primary Examiner(s): Quach; Tuan N.
• Application Number:
  US12/288,009
• Publication Number:
  US 20090142872A1
• Time in Patent Office: 623 Days
• Field of Search: 438/48, 438/50, 438/53, 438/438, 438/444, 257/E21.211
• US Class Current: 438/50
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type

Abstract

The current invention provides methods of fabricating a capacitive micromachined ultrasonic transducer (CMUT) that includes oxidizing a substrate to form an oxide layer on a surface of the substrate having an oxidation-enabling material, depositing and patterning an oxidation-blocking layer to form a post region and a cavity region on the substrate surface and remove the oxidation-blocking layer and oxide layer at the post region. The invention further includes thermally oxidizing the substrate to grow one or more oxide posts from the post region, where the post defines the vertical critical dimension of the device, and bonding a membrane layer onto the post to form a membrane of the device. A maximum allowed second oxidation thickness t₂ can be determined, that is partially based on a desired step height and a device size, and a first oxidation thickness t₁ can be determined that is partially based on the determined thickness t₂.

Claims

1. A method of fabricating a capacitive micromachined ultrasonic transducer (CMUT), said method comprising:

(a) depositing an oxidation-blocking layer onto a substrate, wherein said substrate comprises an oxidation-enable material;

(b) patterning said oxidation-blocking layer, wherein said patterning forms a post region and a cavity region of a surface of said substrate, and wherein said patterning removes said oxidation-blocking layer from said substrate at said post region;

(c) thermally oxidizing said substrate, wherein said thermally oxidizing grows one or more oxide posts from said post region, and wherein said post defines a vertical dimension of said CMUT; and

(d) bonding a membrane layer onto said post, wherein said membrane layer forms a membrane of said CMUT.

2. The method as set forth in claim 1, further comprising oxidizing said substrate before depositing said oxidation-blocking layer onto said substrate, wherein said oxidizing forms an oxide layer on a surface of said substrate, and wherein said patterning removes said oxide layer from said substrate at said post region.

3. The method as set forth in claim 2, further comprising removing some of said oxide layer located at or near the boundary of said post and said cavity region to define a horizontal size of said CMUT.

4. The method as set forth in claim 2, wherein said patterning comprises:

(i) etching said oxidation-blocking layer by wet or dry etching; and

(ii) etching said oxide layer by wet etching.

5. The method as set forth in claim 1, wherein said thermally oxidizing said substrate to grow said post forms a protrusion of said oxidation-blocking layer.

6. The method as set forth in claim 5, further comprising removing said protrusion of said oxidation-blocking.

7. The method as set forth in claim 1, further comprising removing approximately all of said oxidation-blocking layer from said cavity region.

8. The method as set forth in claim 7, further comprising removing some of said oxide layer located at or near the boundary of said post and said cavity region to define a horizontal size of said CMUT.

9. The method as set forth in claim 1, wherein said substrate initially comprises a substrate step, and wherein said cavity region to be formed from said patterning at least partially overlaps with said substrate step.

10. The method as set forth in claim 1, further comprising introducing a substrate step to said substrate before depositing said oxidation-blocking layer onto said substrate, wherein said step introducing comprises:

(i) thermally oxidizing said substrate to form an oxide layer on said surface of said substrate;

(ii) patterning said oxide layer to form an open region and a step region, wherein said patterning removes said oxide layer from said substrate at said open region;

(iii) thermally oxidizing said substrate and said patterned oxide layer; and

(iv) removing approximately all of said oxide, whereby said substrate remaining has said substrate step,

wherein said thermally oxidizing in (i) is referred to as a first oxidizing step and is associated with a first oxidation thickness t, and wherein said thermally oxidizing in (iii) is referred to as a second oxidizing step and is associated with a second oxidation thickness t₂.

11. The method as set forth in claim 10, further comprising:

determining a maximum allowed value for t₂ based on a desired height of said substrate step and a horizontal size of said CMUT; and

calculating a value for t₁, based on said maximum allowed value of t₂,

wherein said first oxidizing forms said oxide layer having a thickness approximately equal to said calculated value of t₁, and wherein said second oxidizing is based on said maximum allowed value of t₂.

12. The method as set forth in claim 1, further comprising introducing a substrate step to said substrate before depositing said oxidation-blocking layer onto said substrate, wherein said step introducing comprises:

(i) depositing a temporary oxidation-blocking layer onto said substrate;

(ii) patterning said temporary oxidation-blocking layer to form an open region and a step region, wherein said patterning removes said temporary oxidation-blocking layer from said substrate at said open region;

(iii) thermally oxidizing said substrate, wherein said thermally oxidizing consumes said oxidation-enable material of said substrate at said open region, and wherein said thermally oxidizing grows one or more temporary oxide posts at said post region; and

(iv) removing approximately all of said temporary oxidation-blocking layer and said temporary oxide posts, whereby said substrate remaining has said substrate step.

13. The method as set forth in claim 12, further comprising oxidizing said substrate before depositing said temporary oxidation-blocking layer onto said substrate, wherein said oxidizing forms an oxide layer on a surface of said substrate, and wherein said patterning removes said oxide layer from said substrate at said open region.

14. The method as set forth in claim 1, wherein said substrate comprises silicon, and wherein said silicon substrate has a surface having a low surface roughness.

15. The method as set forth in claim 1, wherein said oxidation-blocking layer comprises silicon nitride.

16. The method as set forth in claim 1, wherein said membrane layer comprises a material selected from a group consisting of single crystal silicon, polysilicon, silicon carbide, diamond, metal, and silicon nitride.

17. The method as set forth in claim 1, wherein said bonding said membrane layer comprises direct wafer bonding or fusion bonding.

18. The method as set forth in claim 1, wherein said membrane layer is bonded to a top surface of said post, wherein said top surface of said post has a low surface roughness, and wherein said low surface roughness has a root mean square surface deviation less than about 2 nm.

19. A method of fabricating a step on a substrate of a device, wherein said substrate comprises an oxidation-enable material, said method comprising:

(a) determining a maximum allowed second oxidation thickness t₂, wherein said determining is at least partially based on a desired height of said step and a size of said device;

(b) calculating a first oxidation thickness t₁, wherein said calculating is at least partially based on said determined maximum allowed t₂;

(c) thermally oxidizing said substrate to form an oxide layer on a surface of said substrate, wherein the thickness of said oxide layer is based on said calculated t₁;

(d) patterning said oxide layer to form an open region and a step region, wherein said patterning removes said oxide layer from said substrate at said open region;

(e) thermally oxidizing said substrate and said patterned oxide layer based on said maximum allowed t₂; and

(f) removing approximately all of said oxide, whereby said substrate remaining has a step.

20. The method as set forth in claim 19, wherein said device is a capacitive micromachined ultrasonic transducer (CMUT), and wherein said maximum allowed t₂ is determined at least partially based on a horizontal size of said CMUT.

21. The method as set forth in claim 19, wherein said maximum allowed t₂ ranges from about 10 nm to about 30 μ

m, and wherein said calculated t₁ ranges from about 10 nm to about 30 μ

m.

22. The method as set forth in claim 19, wherein said removing approximately all of said oxide comprises etching approximately all of said oxide, wherein said etching comprises over-etching said oxide at said open region for an over-etch time, and wherein said over-etch time is at least partially based on said maximum allowed t₂ and said calculated t₁.

23. A method of fabricating a device having a vertical critical dimension, said method comprising:

(a) oxidizing a substrate to form an oxide layer on a surface of said substrate, wherein said substrate comprises an oxidation-enable material;

(b) depositing an oxidation-blocking layer on said oxide layer;

(c) patterning said oxidation-blocking layer and said oxide layer, wherein said patterning forms a post region and a cavity region of said surface of said substrate, and wherein said patterning removes said oxidation-blocking layer and said oxide layer from said substrate at said post region;

(d) thermally oxidizing said substrate, wherein said thermally oxidizing grows one or more oxide posts from said post region, and wherein said post defines said vertical critical dimension of said device; and

(e) bonding a membrane layer onto said post, wherein said membrane layer forms a membrane of said device.