Image sensor and method for manufacturing the same

• US 7,745,250 B2
• Filed: 12/26/2007
• Issued: 06/29/2010
• Est. Priority Date: 12/27/2006
• Status: Active Grant

• Current Assignee: Intellectual Discovery Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Han, Jae Won
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/964,415
• Publication Number:
  US 20080210982A1
• Time in Patent Office: 916 Days
• Field of Search: 438/57, 438/70, 438/74, 438/75, 438/381, 257/292, 257/440
• US Class Current: 438/57
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration

Abstract

An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the circuit part of the second wafer.

Claims

1. A method for manufacturing an image sensor, comprising:

providing a first wafer provided with a photodiode cell without a microlens, wherein providing the first wafer provided with the photodiode cell without the microlens comprises;

forming the photodiode cell on a first semiconductor substrate of the first wafer;

forming a penetrating electrode in the first semiconductor substrate and connected to the photodiode cell; and

forming a color filter on the photodiode cell and the penetrating electrode;

providing a second wafer provided with a transistor and a capacitor;

stacking the first wafer on the second wafer; and

electrically connecting the photodiode cell to the transistor and the capacitor.

2. The method according to claim 1, wherein the photodiode cell and the circuit part are electrically connected through a connecting electrode.

3. The method according to claim 1, wherein providing the first wafer provided with the photodiode cell without the microlens further comprises exposing the penetrating electrode at a lower side of the first wafer after forming the color filter.

4. The method according to claim 1, wherein electrically connecting the photodiode cell to the transistor and the capacitor uses a connecting electrode electrically connected to the photodiode cell through the penetrating electrode.

5. The method according to claim 1, wherein the penetrating electrode comprises W, Cu, Al, Ag, or Au.

6. The method according to claim 1, wherein providing the first wafer provided with the photodiode cell without the microlens further comprises forming a barrier metal between the first semiconductor substrate and the penetrating electrode.

7. The method according to claim 6, wherein the barrier metal is formed of Ti, TiN, Ti/TiN, Ta, TaN, Ta/TaN, TaN/Ta, Co, Co-compound, Co-nitride, Ni, Ni-compound, Ni-nitride W, W-compound, or W-nitride.

8. The method according to claim 1, wherein providing the second wafer provided with the transistor and the capacitor comprises:

forming a transistor on a first region of a second semiconductor substrate of the second wafer;

forming a metal line on the second wafer provided with the transistor and forming a lower electrode of the capacitor on a second region of the second semiconductor substrate of the second wafer provided with the transistor;

forming an interlayer dielectric layer on the metal line and the lower electrode; and

forming an upper electrode on the interlayer dielectric layer on the upper side of the lower electrode.

9. The method according to claim 8, wherein after the step of forming the upper electrode, the providing the second wafer provided with the transistor and the capacitor further comprises:

forming an insulating layer over the second wafer provided with the upper electrode;

forming a top electrode on the insulating layer;

forming a protective layer on the top electrode; and

forming a pad opening through the protective layer.

10. The method according to claim 9, wherein the pad opening is formed in the second wafer to correspond to a position of an exposed penetrating electrode of the first wafer.

11. The method according to claim 8, wherein forming the interlayer dielectric layer on the metal line and the lower electrode comprises:

forming an initial interlayer dielectric layer on the metal line and the lower electrode; and

performing a planarization process until the initial interlayer dielectric layer has a thickness suitable for the capacitor capacity.

12. The method according to claim 8, wherein forming the interlayer dielectric layer on the metal line and the lower electrode comprises:

forming a dummy interlayer dielectric layer on the metal line and the lower electrode;

performing a planarization process on the dummy interlayer dielectric layer until the lower electrode is exposed; and

forming a second interlayer dielectric layer at a thickness suitable for the capacitor capacity on the exposed lower electrode.