MOSFET performance improvement using deformation in SOI structure

• US 7,745,277 B2
• Filed: 02/25/2005
• Issued: 06/29/2010
• Est. Priority Date: 09/12/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Dokumaci, Omer H.
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US11/065,061
• Publication Number:
  US 20050142788A1
• Time in Patent Office: 1,950 Days
• Field of Search: 438275-308, 438310-311, 438199-202, 257/E21.633
• US Class Current: 438/199
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor layer on a substrate. The first region of the substrate is expanded to push up the first portion of the semiconductor layer, thereby applying tensile stress to the first portion. The second region of the substrate is compressed to pull down the second portion of the semiconductor layer, thereby applying compressive stress to the second portion. An N type device is formed over the first portion of the semiconductor layer, and a P type device is formed over the second portion of the semiconductor layer.

Claims

1. A method for manufacturing a semiconductor device, comprising steps of:

forming a buried oxide layer on a silicon substrate;

forming a semiconductor layer on the buried oxide layer such that the buried oxide layer is disposed between the semiconductor layer and the substrate;

performing a first ion-implanting step of an expansion element in a first region of the substrate while masking a second region of the substrate;

performing a second ion-implanting step of a compression element in the second region of the substrate while masking the first region of the substrate, wherein the second ion-implanting step is separate from the first ion-implanting step;

expanding the expansion element to expand the first region of the substrate to push up a first portion of the semiconductor layer and a first portion of the buried oxide layer;

compressing the compression element to compress the second region of the substrate to pull down a second portion of the semiconductor layer and a second portion of the buried oxide layer;

forming a first gate oxide layer of an N type device on the first portion of the semiconductor layer;

forming a first gate electrode on the first gate oxide layer;

forming a second gate oxide layer of a P type device on the second portion of the semiconductor layer; and

forming a second gate electrode on the second gate oxide layer.

2. The method of claim 1, wherein the step of expanding the first region comprises a step of ion-implanting the expansion element in the first region of the substrate.

3. The method of claim 2, wherein the expansion element is ion-implanted at an implantation concentration of approximately 1×

10¹⁴ atoms/cm² to 5×

10¹⁶ atoms/cm² and at an implantation energy of approximately 30 KeV to 300 KeV.

4. The method of claim 2, wherein a concentration peak of the implanted expansion element is confined within the first region.

5. The method of claim 3, wherein the expansion element is O₂.

6. The method of claim 1, wherein the step of compressing the second region comprises a step of ion-implanting the compression element in the second region of the substrate.

7. The method of claim 6, wherein the compression element is ion-implanted at an implantation concentration of approximately 1×

10¹⁴ atoms/cm² to 5 ×

10¹⁶atoms/cm² at an implantation energy of approximately 30 KeV to 300 KeV.

8. The method of claim 6, wherein a concentration peak of the implanted compression element is confined within the second region.

9. The method of claim 6, wherein the compression element is He, Ar, or noble gas.

15. The method of claim 1, wherein:

the step of expanding the first region comprises ion-implanting the expansion element in the first region of the substrate and annealing to activate the expansion element; and

the step of compressing the second region comprises ion-implanting the compression element in the second region of the substrate and annealing to activate the compression element.

16. The method of claim 15, wherein

the expanding the first region pushes up the first portion of the buried oxide layer and the first portion of the semiconductor layer thereby increasing tensile stress in the first portion if the semiconductor layer, and

the compressing the second region pulls down the second portion of the buried oxide layer and the second portion of the semiconductor layer thereby increasing the compressive stress in the second portion of the semiconductor layer.

19. The method of claim 1, further comprising:

forming a shallow trench isolation region in the semiconductor layer between the first portion of the semiconductor layer and the second portion of the semiconductor layer; and

annealing to activate the expansion element and the compression element, wherein the annealing causes the expanding and the compressing;

wherein the performing the first ion-implanting step comprises;

forming a first mask layer on the semiconductor layer, wherein the first mask layer selectively exposes the first portion of the semiconductor layer and masks the second portion of the semiconductor layer;

ion-implanting the expansion element through an opening in the first mask layer, through the semiconductor layer, through the buried oxide layer, and into the first region of the substrate; and

removing the first mask layer;

the performing the second ion-implanting step comprises;

forming a second mask layer on the semiconductor layer, wherein the second mask layer selectively exposes the second portion of the semiconductor layer and masks the first portion of the semiconductor layer;

ion-implanting the compression element through an opening in the second mask layer, through the semiconductor layer, through the buried oxide layer, and into the second region of the substrate; and

removing the second mask layer;

the forming the first gate oxide layer is performed after the expanding, such that the first portion of the semiconductor layer and the first portion of the buried oxide layer are pushed up prior to the first gate oxide layer being formed; and

the forming the second gate oxide layer is performed after the compressing, such that the second portion of the semiconductor layer and the second portion of the buried oxide layer are pulled down prior to the second gate oxide layer being formed.

10. A method for manufacturing a semiconductor device, comprising steps of:

forming a buried oxide layer on a silicon substrate;

forming a semiconductor layer on the buried oxide layer, wherein the buried oxide layer is disposed between the semiconductor layer and the substrate;

performing a first ion-implanting step of an expansion element in a first region of the substrate while masking a second region of the substrate;

performing a second ion-implanting step of a compression element in the second region of the substrate while masking the first region of the substrate, wherein the second ion-implanting step is separate from the first ion-implanting step;

expanding the expansion element to expand the first region of the substrate to provide a tensile stress in the semiconductor layer;

compressing the second region of the substrate to provide a compressive stress in the semiconductor layer by annealing to activate the compression element;

after the expanding, forming a first gate oxide layer of an N type device on the semiconductor layer over the first region of the substrate;

forming a first gate electrode on the first gate oxide layer;

after the compressing, forming a second gate oxide layer of a P type device on the semiconductor layer over the second region of the substrate; and

forming a second gate electrode on the second gate oxide layer,

wherein the expanding pushes up a first portion of the buried oxide layer; and

the compressing pulls down a second portion of the buried oxide layer.

11. The method of claim 10, wherein the compression element is ion-implanted at an implantation concentration of approximately 1×

10 atoms/cm² to 5×

10¹⁶atoms/cm² and at an implantation energy of approximately 30 KeV to 300 KeV.

12. The method of claim 10, wherein the step of expanding the first region comprises a step of ion-implanting the expansion element in the first region of the substrate.

13. The method of claim 12, wherein the expansion element is ion-implanted at an implantation concentration of approximately 1×

10¹⁴ atoms/cm² to 5×

10¹⁶atoms/cm² and at an implantation energy of approximately 30 KeV to 300 KeV.

14. The method of claim 12, wherein the expansion element is O₂and the compression element is He, Ar, or noble gas.

17. The method of claim 10, wherein the step of expanding the first region comprises ion-implanting the expansion element in the first region of the substrate and annealing to activate the expansion element.

18. The method of claim 17, wherein

the expanding the first region pushes up the first portion of the buried oxide layer and a first portion of the semiconductor layer thereby increasing tensile stress in the first portion of the semiconductor layer, and

the compressing the second region pulls down the second portion of the buried oxide layer and a second portion of the semiconductor layer thereby increasing the compressive stress in the second portion of the semiconductor layer.