Capacitor that includes high permittivity capacitor dielectric

• US 7,745,279 B2
• Filed: 01/13/2006
• Issued: 06/29/2010
• Est. Priority Date: 07/25/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Hu, Chenming
• Primary Examiner(s): Doan; Theresa T
• Application Number:
  US11/331,703
• Publication Number:
  US 20060124965A1
• Time in Patent Office: 1,628 Days
• Field of Search: 438238-240, 257/516, 257/532, 257E21382-E21385
• US Class Current: 438/239
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

Claims

1. A method of forming a decoupling capacitor, the method comprising:

providing a semiconductor substrate that includes a silicon surface layer;

forming a substantially flat bottom electrode in a portion of the silicon surface layer, the bottom electrode being doped to a first conductivity type;

pre-treating the bottom electrode with a non-metal gas prior to forming an interfacial layer between the bottom electrode and a high permittivity capacitor dielectric;

forming the interfacial layer over the pre-treated surface of the bottom electrode;

simultaneously forming the high permittivity capacitor dielectric and a gate dielectric from a high permittivity dielectric with a relative permittivity greater than about 5, the high permittivity capacitor dielectric formed over the interfacial layer;

forming a substantially flat top electrode over the high permittivity capacitor dielectric;

forming a doped region within the silicon surface layer adjacent to the bottom electrode, the doped region doped to a second conductivity type;

electrically coupling the top electrode to a first reference voltage line; and

electrically coupling the bottom electrode to a second reference voltage line.

2. The method of claim 1, wherein the non-metal gas is comprised of hydrogen.

3. The method of claim 1, wherein the non-metal gas is comprised of nitrogen.

4. The method of claim 1, wherein the interfacial layer is comprised of silicon oxide.

5. The method of claim 1, wherein the interfacial layer is comprised of silicon oxynitride.

6. The method of claim 1, wherein the bottom electrode is doped to a concentration greater than or equal to 1E19 cm⁻

3.