Methods of forming semiconductor devices

• US 7,745,286 B2
• Filed: 07/16/2007
• Issued: 06/29/2010
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Chih-Hsin Wang
• Inventors: Wang, Chih-Hsin
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US11/879,090
• Publication Number:
  US 20070281425A1
• Time in Patent Office: 1,079 Days
• Field of Search: 438257-258, 438593-594, 438/201
• US Class Current: 438/257
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the channel; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a filter adjacent to the first conductive region; and arranging a second conductive region adjacent to the filter. The second conductive region overlaps the first conductive region at an overlap surface. A line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

Claims

1. A method of forming a memory cell, the method comprising:

forming a body of a first conductivity type in a semiconductor substrate;

forming a first insulator layer adjacent to the substrate;

forming a charge storage region adjacent to the first insulator layer;

forming first and second regions of a second conductivity type in the body;

forming a channel region in the body between the first region and the second region, and generally disposed adjacent to and insulated from the charge storage region;

forming a second insulator layer adjacent to the charge storage region;

forming a first electrically conductive region comprising at least a portion thereof disposed adjacent to and insulated from the charge storage region by the second insulator layer;

forming a filter comprising a filtering function adjacent to the first electrically conductive region; and

forming a second electrically conductive region adjacent to and insulated from at least a portion of the first electrically conductive region by the filter,

wherein the second electrically conductive region has charge carriers with an energy distribution and overlaps with the first electrically conductive region at an overlap surface, and

wherein a line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

2. The method of claim 1, wherein the at least a portion of the charge storage region is disposed under the overlap surface.

3. The method of claim 1, wherein the filter includes:

a multi-layer dielectric; and

a voltage-divider function for reducing voltage drops in the multi-layer dielectric.

4. The method of claim 1, wherein the filtering function includes at least one function selected from a group consisting of:

band-pass filtering, mass-filtering, and charge-filtering.

5. The method of claim 1, wherein forming the filter comprises:

forming a first dielectric adjacent to the second electrically conductive region; and

forming a second dielectric adjacent to the first dielectric,

wherein the second dielectric has an energy band gap narrower than an energy band gap of the first dielectric.

6. The method of claim 5, wherein a product of a dielectric constant of the second dielectric and a thickness of the first dielectric is substantially greater than a product of a dielectric constant of the first dielectric and a thickness of the second dielectric.

7. The method of claim 5, wherein the first dielectric comprises oxide, and

wherein the second dielectric comprises a material selected from the group consisting of:

nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

8. The method of claim 5, wherein the first dielectric comprises oxynitride, and

wherein the second dielectric comprises a material selected from the group consisting of:

nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

9. The method of claim 7, wherein the oxide is formed using at least one technique selected from the group consisting of thermal oxidation, HTO, TEOS, and ISSG.

10. The method of claim 1, further comprising forming a strain source that provides mechanical stress to at least one of the first and second electrically conductive regions.

11. The method of claim 10, wherein the strain source comprises a material selected from the group consisting of:

thermal-CVD nitride, plasma-CVD nitride, tungsten-silicide, amorphous silicon, poly SiGe, TaN, and TiN.

12. The method of claim 10, wherein the strain source imposes a compressive stress.

13. The method of claim 10, wherein the strain source imposes a tensile stress.

14. The method of claim 10, further comprising ion implanting one or more impurities into the strain source for tailoring a stress level of the mechanical stress.

15. The method of claim 10, wherein the strain source comprises dislocation loops in at least one of the first and second electrically conductive regions.

16. The method of claim 15, further comprising ion implanting atoms at a predetermined dosage into at least one of the first and second electrically conductive regions.

17. The method of claim 16, wherein the atoms comprise at least one material selected from the group consisting of:

Si, Ge, As, and nitrogen.

18. The method of claim 1, wherein the forming the first and second regions is performed before the forming of the first insulator layer adjacent to the substrate.

19. The method of claim 1, wherein the forming the first and second regions is performed after the forming of the charge storage region adjacent to the first insulator.

20. A method of providing an array of memory cells, the method comprising:

forming a body of a first conductivity type in a semiconductor substrate;

forming a first insulator layer adjacent to the substrate;

forming a plurality of charge storage regions adjacent to the first insulator layer and arranged in an array of columns extending in a first direction and rows in a second direction generally perpendicular to the first direction;

forming a plurality of first regions of a second conductivity type;

forming a plurality of second regions of the second conductivity type;

forming a plurality of channel regions in the body each extending between one of the first regions and one of the second regions, and generally disposed adjacent to and insulated from one of the charge storage regions;

forming a second insulator layer adjacent to each of the charge storage regions;

forming a plurality of first electrically conductive regions each comprising at least a portion thereof disposed adjacent to and insulated from one of the charge storage regions by the second insulator layer;

forming a plurality of filters comprising a filtering function each comprising at least a portion disposed adjacent to one of the first electrically conductive regions;

forming a plurality of second electrically conductive regions each comprising charge carriers with an energy distribution and each disposed adjacent to and insulated from at least a portion of one of the first electrically conductive regions by one of the filters; and

forming a plurality of parallel spaced apart bit-lines extending in the first direction with at least one of the bit-lines electrically connected to at least one of the second regions,

wherein each of the first electrically conductive regions overlaps with one of the second electrically conductive regions at an overlap surface, and wherein lines perpendicular to the overlap surfaces intersect at least part of corresponding ones of the charge storage regions.

21. The method of claim 20, further comprising:

forming a plurality of parallel spaced apart word-lines of conductive material each extending across the bit-lines in the second direction,

wherein each of the word-lines is electrically connected to at least one of the first electrically conductive regions; and

forming a plurality of parallel spaced apart tunneling-lines of conductive material, each of the plurality of parallel spaced apart tunneling-lines extending in the first direction and electrically connected to at least one of the second electrically conductive regions.

22. The method of claim 21, further comprising forming a plurality of oxide line blocks interlaced with the word-lines.

23. The method of claim 20, wherein the at least part of the charge storage regions is disposed under a corresponding one of the overlap surfaces.

24. The method of claim 20, wherein each of the bit-lines is formed in at least a portion of the body.

25. The method of claim 20, wherein at least one of the bit-lines is electrically connected to at least one of the first regions.

26. The method of claim 20, wherein each of the filters includes:

a multi-layer dielectric; and

a voltage-divider function for reducing voltage drops in the multi-layer dielectric.

27. The method of claim 20 wherein each of the filtering functions includes at least one filtering function selected from a group consisting of:

band-pass filtering, mass-filtering, and charge-filtering.

28. The method of claim 20, wherein the forming of the plurality of filters comprises:

forming a plurality of first dielectrics each adjacent to one of the second electrically conductive regions; and

forming a plurality of second dielectrics each adjacent to one of the first dielectrics,

wherein each of the second dielectrics has an energy band gap narrower than an energy band gap of each of the first dielectrics.

29. The method of claim 28, wherein a product of a dielectric constant of each of the second dielectrics and a thickness of each of the first dielectrics is substantially greater than a product of a dielectric constant of each of the first dielectrics and a thickness of each of the second dielectrics.

30. The method of claim 28, wherein each of the first dielectrics comprises oxide, and

wherein each of the second dielectrics comprises a material selected from the group consisting of:

nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

31. The method of claim 28, wherein each of the first dielectrics comprises oxynitride, and

wherein each of the second dielectrics comprises a material selected from the group consisting of:

nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

32. The method of claim 20, further comprising forming a plurality of strain sources, each strain source providing a mechanical stress to at least one of the first and second electrically conductive regions.

33. The method of claim 32, wherein each of the strain sources comprises a material selected from the group consisting of:

thermal-CVD nitride, plasma-CVD nitride, tungsten-silicide, amorphous silicon, poly SiGe, TaN, and TiN.

34. The method of claim 32, wherein each of the strain sources imposes a compressive stress.

35. The method of claim 32, wherein each of the strain sources imposes a tensile stress.

36. The method of claim 20, wherein the forming of the plurality of first and second regions is performed before the forming of the first insulator layer adjacent to the substrate.

37. The method of claim 20, wherein the forming of the plurality of first and second regions is performed after the forming of the plurality of charge storage regions adjacent to the first insulator.

38. A method of providing a memory cell, the method comprising:

providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions;

arranging a first insulator layer adjacent to the channel;

arranging a charge storage region adjacent to the first insulator layer;

arranging a second insulator layer adjacent to the charge storage region;

arranging a first conductive region adjacent to the second insulator layer;

arranging a filter adjacent to the first conductive region; and

arranging a second conductive region adjacent to the filter,

wherein the second conductive region overlaps the first conductive region at an overlap surface, and

wherein a line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

39. The method of claim 38, wherein the at least a portion of the charge storage region is disposed under the overlap surface.

40. The method of claim 38, wherein the filter includes a multi-layer dielectric.

41. The method of claim 38, further comprising performing at least one of:

band-pass filtering, mass-filtering, and charge-filtering using the filter.

42. The method of claim 38, wherein arranging the filter comprises:

arranging a first dielectric adjacent to the second conductive region; and

arranging a second dielectric adjacent to the first dielectric.

43. The method of claim 42, further comprising selecting an energy band gap of the second dielectric that is narrower than an energy band gap of the first dielectric.

44. The method of claim 43, wherein a first product of a dielectric constant of the second dielectric and a thickness of the first dielectric is substantially greater than a second product of a dielectric constant of the first dielectric and a thickness of the second dielectric.

45. The method of claim 42, wherein the first dielectric comprises oxide, and

wherein the second dielectric comprises a material selected from the group consisting of:

nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

46. The method of claim 42, wherein the first dielectric comprises oxynitride, and

wherein the second dielectric comprises a material selected from the group consisting of:

nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

47. The method of claim 45, wherein the oxide is formed using at least one technique selected from the group consisting of:

thermal oxidation, HTO, TEOS, and ISSG.

48. The method of claim 38, wherein the charge storage region comprises a plurality of spaced-apart nano-particles.

49. The method of claim 38, wherein the charge storage region comprises a trapping dielectric including a plurality of trapping centers.