Method of forming a FET having ultra-low on-resistance and low gate charge

• US 7,745,289 B2
• Filed: 11/24/2004
• Issued: 06/29/2010
• Est. Priority Date: 08/16/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok, Mo, Brian Sze-Ki, Bencuya, Izak
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Garcia; Joannie A
• Application Number:
  US10/997,818
• Publication Number:
  US 20050153497A1
• Time in Patent Office: 2,043 Days
• Field of Search: 438/156, 438/212, 438/268, 438/269, 438/270, 438/272, 438/FOR.192, 438/FOR.176, 257/328, 257/329, 257/330, 257/331, 257/334
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

Claims

1. A method of forming a field effect transistor, comprising:

epitaxially forming a substrate cap region of a first conductivity type silicon over and in contact with a substrate of the first conductivity type silicon;

epitaxially forming a body region of a second conductivity type silicon over and in contact with the substrate cap region;

forming a plurality of trenches each extending at least through the body region;

lining the sidewalls and bottom of each trench with a dielectric material;

at least partially filling each trench with a conductive material; and

forming a plurality of source regions of the first conductivity type in an upper portion of the body region,

wherein during one or more temperature cycles, dopants of the first conductivity type in the substrate cap region out-diffuse into a lower portion of the body region to form an out-diffusion region of the first conductivity type extending from an interface between the body region and the substrate cap region into the body region such that a spacing between the source regions and the out-diffusion region defines a length of a channel region of the field effect transistor.

2. The method of claim 1 wherein:

each trench extends through the out-diffusion region, and

the conductive material in each trench extends through a substantial depth of the out-diffusion region.

3. The method of claim 1 wherein during the one or more temperature cycles the substrate cap region influences said out-diffusion of the dopants of the first conductivity type into the body region such that the length of the channel region varies less and is thus substantially predictable.

4. The method of claim 1 wherein the substrate cap region has a thickness less than or equal to 2 μ

m.

5. The method of claim 1 wherein the out-diffusion region has a graded doping concentration decreasing in a direction away from an interface between the out-diffusion region and the substrate cap region.

6. A method of forming a field effect transistor, comprising:

providing a substrate of a first conductivity type silicon;

forming a substrate cap region of the first conductivity type silicon such that a junction is formed between the substrate cap region and the substrate;

forming an epitaxial layer of the first conductivity type silicon over the substrate cap region;

implanting dopants of a second conductivity type into the epitaxial layer and driving the dopants into the epitaxial layer to thereby form a body region having a junction with the substrate cap region;

forming a plurality of trenches each extending at least through the body region;

lining the sidewalls and bottom of each trench with a dielectric material;

at least partially filling each trench with a conductive material; and

forming a plurality of source regions of the first conductivity type in an upper portion of the body region,

wherein during one or more temperature cycles, dopants of the first conductivity type in the substrate cap region out-diffuse into a lower portion of the body region to form an out-diffusion region of the first conductivity type extending from the junction between the body region and the substrate cap region into the body region such that a spacing between the source regions and the out-diffusion region defines a length of a channel region of the field effect transistor.

7. The method of claim 6 wherein the substrate cap region is epitaxially formed over and in contact with the substrate.

8. The method of claim 6 wherein the substrate cap region is formed in the substrate by implanting dopants of the first conductivity type into the substrate.

9. A field effect transistor, comprising:

a substrate of a first conductivity type silicon;

an epitaxial substrate cap region of the first conductivity type silicon over and in contact with the substrate;

an epitaxial body region of a second conductivity type over and in contact with the substrate cap region;

a plurality of trenches each extending at least through the body region;

a dielectric material lining the sidewalls and bottom of each trench;

a conductive material at least partially filling each trench;

a plurality of source regions of the first conductivity type in an upper portion of the body region; and

an out-diffusion region of the first conductivity type extending from an interface between the body region and the substrate cap region into the body region such that a spacing between each source region and the out-diffusion region defines a length of a channel region of the field effect transistor, the channel region extending vertically along a sidewall of each trench.

10. The field effect transistor of claim 9 wherein:

each trench extends through the out-diffusion region, and

the conductive material in each trench extends through a substantial depth of the out-diffusion region.

11. The field effect transistor of claim 9 wherein the dielectric material in each trench is thicker along the bottom of each trench than along the sidewalls of each trench.

12. The field effect transistor of claim 9 wherein the out-diffusion region has a graded doping concentration decreasing in a direction away from an interface between the out-diffusion region and the substrate cap region.

13. The field effect transistor of claim 9 wherein the substrate cap region has a thickness of less than or equal to two micrometers.