Methods and apparatus for high-density chip connectivity

• US 7,745,301 B2
• Filed: 08/21/2006
• Issued: 06/29/2010
• Est. Priority Date: 08/22/2005
• Status: Active Grant

• Current Assignee: Terapede System Inc.
• Original Assignee: Terapede LLC
• Inventors: Vora, Madhukar B.
• Primary Examiner(s): Thai; Luan C
• Application Number:
  US11/507,888
• Publication Number:
  US 20070042529A1
• Time in Patent Office: 1,408 Days
• Field of Search: 438/401, 438/462, 438/108, 438/975, 257/777, 257/E23.179
• US Class Current: 438/401
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: Y10S 438/975 : Substrate or mask aligning feature

Abstract

Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today'"'"'s Ball Grid Array (BGA) technology. As a result, circuits in the mated chips can communicate via the pads with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads. Because high-density arrays of pads can interconnect chips, chips can be made smaller, thereby reducing cost of chips by order(s) of magnitude.

Claims

1. A method of manufacturing a chip, comprising:

forming (i) first electrical components, (ii) a plurality of first conductive pads having first top surfaces with pre-defined dimensions, and (iii) at least one first alignment structure on a first substrate using a first chip manufacturing process, the at least one first alignment structure arranged to be aligned with at least one second alignment structure on a second substrate having a plurality of second conductive pads disposed thereon by a second chip manufacturing process and having second top surfaces with substantially the same dimensions as the first conductive pads;

contacting at least a subset of the first and second top surfaces by aligning the at least one first alignment structure on the first substrate with the at least one second alignment structure on the second substrate; and

causing the at least the subset of the first and second conductive pads to bond together.

2. The method according to claim 1, wherein forming the first alignment structure includes forming an indentation on the first substrate.

3. The method according to claim 2, wherein forming the indentation includes forming an inverted pyramid.

4. The method according to claim 2, wherein forming the indentation includes forming a geometric shape within the substrate configured to provide self-alignment with a differently shaped at least one second alignment structure formed on the second chip or with a separate component configured to be disposed within the geometric shape.

5. The method according to claim 1, wherein forming the conductive pads includes forming conductive pads having a pitch less than approximately 100 microns.

6. The method according to claim 1, wherein forming the conductive pads includes forming conductive pads having a pitch less than approximately 10 microns.

7. The method according to claim 1, wherein forming the conductive pads includes forming conductive pads having a pitch less than approximately 1 micron.

8. The method according to claim 1, wherein forming the conductive pads includes forming conductive pads having a surface area less than approximately 10 square microns.

9. A method for aligning a first and a second chip, said method comprising:

contacting at least one first self-alignment feature of a first chip with at least one second self-alignment feature of a second chip, the first chip and second chip having a plurality of conductive pads having top surfaces of approximately the same dimensions; and

moving the first and second chips relative to each other to enable the at least one first and second self alignment features to self align in a manner causing at least a subset of the top surfaces of the first and second conductive pads to contact one another.

10. The method according to claim 9, wherein said moving is performed along a plane and the self-alignment of the at least one first and second self alignment features is performed in a direction other than along the plane.

11. The method according to claim 9, wherein moving the first and second chips relative to each other enables the at least one first and second self alignment features to gravitationally self-align.

12. The method according to claim 9, wherein contacting the at least one first self-alignment feature of the first chip with the second chip includes contacting at least one semi-hemispheric feature with the second chip.

13. The method according to claim 12, wherein moving the first and second chips relative to each other includes moving the semi-hemispheric feature of the first chip along the second chip until the at least one semi-hemispheric feature slides into at least one indentation having a self aligning geometric shape in the second chip.

14. The method according to claim 9, wherein moving the first and second chips relative to each other includes moving the chips a maximum distance less than 5 microns.

15. The method according to claim 9, wherein moving includes ultrasonically vibrating the two chips to self align the at least one first and second self-alignment features.

16. A method of aligning a first chip with a second chip, said method comprising:

positioning a first chip formed with at least one first alignment feature and a plurality of first conductive pads having first top surfaces with predetermined dimensions;

positioning a second chip formed with at least one second alignment feature and a plurality of second conductive pads having second top surfaces with the substantially same dimensions as the first top surfaces; and

moving at least one of the first and second chips relative to the other chip to align the at least one first and second alignment features to cause at least a subset of the first and second conductive pads to be aligned in a manner such that the respective first and second top surfaces contact one another.

17. The method according to claim 16, wherein moving at least one of the first and second chips relative to the other chip is performed along a plane.

18. The method according to claim 16, wherein moving at least one of the first and second chips relative to the other chip causes the at least one first and second alignment features to self align with respect to one another to cause at least a subset of the first and second conductive pads to contact.

19. The method according to claim 18, wherein moving at least one of the first and second chips relative to the other chip causes the at least one first and second alignment features to gravitationally self align.

20. The method according to claim 16, wherein moving at least one of the first and second chips relative to the other chip causes at least one of the chips to move a maximum of 5 microns.

21. The method according to claim 16, further comprising ultrasonically vibrating the first and second chips to cause the at least one first and second alignment features to self-align.

22. The method according to claim 16, further comprising providing first and second chips having a maximum substrate dimension of approximately 3 square centimeters.

23. A method of communicating signals between chips, comprising:

communicating electrical signals between a first chip and a second chip, the electrical signals passing from a first conductive pad disposed on the first chip to a second conductive pad disposed on the second chip, at least a subset of the first and second conductive pads being in contact with one another and bonded together, and providing for the electrical signals to be communicated between the first and second chips at a clock rate substantially the same as on one of the chips.

24. The method according to claim 23, wherein communicating the electrical signals between the first and second chips via the bonded first and second conductive pads is performed at a minimum rate of approximately 200 MHz.

25. The method according to claim 23, wherein communicating the electrical signals between the first and second chips via the bonded first and second conductive pads is performed at a minimum rate of approximately 1 GHz.

26. The method according to claim 23, wherein communicating the electrical signals between the first and second chips via the bonded first and second conductive pads is performed at a minimum rate of approximately 2 GHz.

27. The method according to claim 23, wherein communicating includes writing data to a memory from the first chip to the second chip via the bonded first and second conductive pads.

28. The method according to claim 27, wherein writing data is performed from the first chip that includes processing functionality.

29. The method according to claim 23, wherein communicating the electrical signals between the first and second chips via the bonded first and second conductive pads is performed between conductive pads having connectivity greater than 1E05 per square centimeter.

30. The method according to claim 23, further comprising automatically determining, by the first chip, the chip type of the second chip.