Method of fabricating micro-vertical structure

• US 7,745,308 B2
• Filed: 04/02/2009
• Issued: 06/29/2010
• Est. Priority Date: 07/08/2008
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute, Gwangju Institute of Science and Technology
• Inventors: Choi, Chang Auck, Lee, Myung Lae, Je, Chang Han, Hwang, Gunn, Lee, Jong Hyun, Jeong, Dae Hun, Yun, Sung Sik, An, Jae Yong
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US12/417,114
• Publication Number:
  US 20100009514A1
• Time in Patent Office: 453 Days
• Field of Search: 438/455, 438/456, 438/700
• US Class Current: 438/455
• CPC Class Codes: B81C 1/00619 Forming high aspect ratio structures having deep steep walls
• CPC Class Codes: B81C 1/00626 Processes for achieving a desired geometry not provided for in groups B81C1/00563 - B81C1/00619
• CPC Class Codes: B81C 2201/0132 Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
• CPC Class Codes: B81C 2201/0133 Wet etching

Abstract

A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes.

Claims

1. A method of fabricating a micro-vertical structure, comprising:

forming an insulating layer on a first crystalline silicon substrate and patterning the insulating layer to form an insulating layer pattern and a first cavity for preventing occurrence of footings;

bonding a second crystalline silicon substrate onto the insulating layer pattern and etching the second crystalline silicon substrate using a deep reactive ion etch (DRIE) process, wherein the second crystalline silicon substrate is etched along a crystal plane vertical to the second crystalline silicon substrate; and

etching an etched vertical surface of the second crystalline silicon substrate using a crystalline wet etching process to form the micro-vertical structure having a vertical surface vertical to the second crystalline silicon substrate.

2. The method according to claim 1, wherein in forming the insulating layer, the insulating layer is patterned such that the first cavity is disposed under an etch end-point of the second crystalline silicon substrate.

3. The method according to claim 1, wherein the forming the insulating layer further comprises etching a partial thickness of the first crystalline silicon substrate to form a support structure and a second cavity after forming the insulating layer pattern and the first cavity.

4. The method according to claim 1, wherein the second crystalline silicon substrate is a (110) crystalline silicon substrate.

5. The method according to claim 4, wherein the crystal plane vertical to the second crystalline silicon substrate is a [111] crystal plane.

6. The method according to claim 1, wherein, reactive ions generated during the DRIE process of the second crystalline silicon substrate are emitted through the first cavity.

7. The method according to claim 1, further comprising depositing an oxide layer on the second crystalline silicon substrate before etching the second crystalline silicon substrate using the crystalline wet etching process.

8. The method according to claim 1, wherein the micro-vertical structure is fixed to the first crystalline silicon substrate by the insulating layer pattern.

9. The method according to claim 1, further comprising removing the insulating layer pattern to float the micro-vertical structure.