Method for reducing silicide defects in integrated circuits
First Claim
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1. A method for forming a transistor in an integrated circuit (IC) comprising:
- providing a substrate having a gate on the substrate, the gate having gate sidewalls, and diffusion regions in the substrate adjacent to the gate;
forming dielectric spacers on the gate sidewalls;
forming metal silicide contacts over the diffusion regions, wherein portions of the metal silicide contacts are covered by the spacers; and
pulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts to reduce stress on the metal silicide contacts.
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Abstract
A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
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Citations
21 Claims
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1. A method for forming a transistor in an integrated circuit (IC) comprising:
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providing a substrate having a gate on the substrate, the gate having gate sidewalls, and diffusion regions in the substrate adjacent to the gate; forming dielectric spacers on the gate sidewalls; forming metal silicide contacts over the diffusion regions, wherein portions of the metal silicide contacts are covered by the spacers; and pulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts to reduce stress on the metal silicide contacts. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for reducing metal pipes comprising:
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providing a feature on a substrate; forming dielectric spacers on sidewalls of the feature;
forming metal silicide contacts on the substrate adjacent to the dielectric spacers, wherein portions of the metal silicide contacts are covered by the spacers; andpulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts, wherein aligning the edges of the dielectric spacers and metal silicide contacts reduces formation of metal pipes. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method of fabricating an integrated circuit comprising:
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providing a semiconductor body having STI, gate and spacer structures; forming a Ni or NiPt layer over the structures; forming TiN cap layer over the structures; forming first phase Ni silicide layer via RIA1 at 300-400°
C., wherein portions of the Ni silicide layer are covered by the spacers;performing wet clean to remove the TiN cap and unreacted Ni; dry (plasma) etching of the spacer to have spacer pull-back, wherein outer walls of the spacers are aligned with edges of the Ni silicide contacts; and forming second phase Ni silicide layer via RTA2 at 400-600°
C. - View Dependent Claims (20, 21)
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Specification