×

Method for reducing silicide defects in integrated circuits

  • US 7,745,320 B2
  • Filed: 05/21/2008
  • Issued: 06/29/2010
  • Est. Priority Date: 05/21/2008
  • Status: Expired due to Fees
First Claim
Patent Images

1. A method for forming a transistor in an integrated circuit (IC) comprising:

  • providing a substrate having a gate on the substrate, the gate having gate sidewalls, and diffusion regions in the substrate adjacent to the gate;

    forming dielectric spacers on the gate sidewalls;

    forming metal silicide contacts over the diffusion regions, wherein portions of the metal silicide contacts are covered by the spacers; and

    pulling back the dielectric spacers, wherein outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts to reduce stress on the metal silicide contacts.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×