Devices and methods for preventing capacitor leakage

• US 7,745,865 B2
• Filed: 07/20/2005
• Issued: 06/29/2010
• Est. Priority Date: 07/20/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tu, Kuo-Chi
• Primary Examiner(s): Louie; Wai-Sing
• Assistant Examiner(s): Montalvo; Eva Y.
• Application Number:
  US11/184,786
• Publication Number:
  US 20070018224A1
• Time in Patent Office: 1,805 Days
• Field of Search: 438/240, 438/239, 438/243, 438/396, 257/296, 257/301, 257/297, 257/E21.651, 257/E21.655, 257/E24.647, 257/E21.653, 257/303, 257/306, 257/71, 257/E27.086, 257/E27.094, 257/E27.092, 257/E29.346, 257/E21.396
• US Class Current: 257/301
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug

Abstract

Devices and methods for preventing capacitor leakage caused by sharp tip. The formation of sharp tip is avoided by a thicker bottom electrode which fully fills a micro-trench that induces formation of the sharp tip. Alternatively, formation of the sharp tip can be avoided by recessing the contact plug to substantially eliminate the micro-trench.

Claims

1. A semiconductor device, comprising:

a contact plug formed in a contact opening through a first insulating layer;

an etch stop layer on the first insulating layer;

a second insulating layer directly on the etch stop layer;

a capacitor landing on the contact plug with an overlay shift, comprising a bottom electrode on the top and sidewall of the contact plug, a capacitor dielectric on the bottom electrode, and a top electrode on the capacitor dielectric;

wherein the second insulating layer defines the height of the capacitor bottom electrode;

wherein one corner of the top surface of the contact plug is covered by the capacitor;

wherein the etch stop layer extends to other three corners of the contact plug not covered by the capacitor; and

wherein the total thickness Z of the bottom electrode and the capacitor dielectric satisfies at least one of the conditions;

Z≧

Y or Z≧

½

X

where X is the distance of the overlay shift, and Y is the height of the sidewall of the contact plug covered by the bottom electrode.

2. The semiconductor device of claim 1, wherein the contact plug is formed over a source/drain region of a MOSFET transistor.

3. The semiconductor device of claim 1, wherein the capacitor is a cup-shaped capacitor.

4. The semiconductor device of claim 1, wherein the etch stop layer is a single-layered etch stop layer.