Dual work function metal gate structure and related method of manufacture

• US 7,745,887 B2
• Filed: 09/27/2007
• Issued: 06/29/2010
• Est. Priority Date: 02/22/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min-Joo, Han, Sungkee, Lee, Jong-Ho, Jung, Hyung-Suk
• Primary Examiner(s): Sarkar; Asok K
• Application Number:
  US11/862,404
• Publication Number:
  US 20080017930A1
• Time in Patent Office: 1,006 Days
• Field of Search: 257/407, 257/E21.632, 438/199
• US Class Current: 257/407
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine.

Claims

1. A semiconductor device, comprising at least one of:

a NMOS metal gate structure comprising a first metal gate electrode formed from a metal layer doped with fluorine to have a first work function; and

,

a PMOS metal gate structure comprising a second metal gate electrode formed from the metal layer doped with carbon to have a second work function.

2. The semiconductor device of claim 1, wherein the second work function is greater than the first work function.

3. The semiconductor device of claim 1, wherein the metal layer is doped with a Gaussian concentration profile of carbon atoms along the thickness of the metal layer.

4. The semiconductor device of claim 1, wherein the metal layer is doped with a Gaussian concentration profile of fluorine atoms along the thickness of the metal layer.

5. The semiconductor device of claim 1, wherein the at least one NMOS and PMOS metal gate structures comprises an additional conductive layer formed on the metal layer to define a profile height for the at least one NMOS and PMOS metal gate structures.

6. The semiconductor device of claim 5, wherein the metal layer is formed to a thickness of less than 100 Å

.

7. The semiconductor device of claim 6, wherein the additional conductive layer is formed to a thickness of greater than 1000 Å

.

8. The semiconductor device of claim 1, wherein the first work function ranges from between about 3.7 to 4.5 eV, and wherein the second work function ranges from between about 4.7 to 5.3 eV.

9. The semiconductor device, comprising:

NMOS and PMOS active regions formed in a substrate;

a gate insulating layer formed on the substrate over the NMOS and PMOS active regions;

a NMOS metal gate structure formed on the gate insulating layer over the NMOS active region and comprising a first metal gate electrode formed from a metal layer and doped with fluorine to have a first work function; and

,

a PMOS metal gate structure formed on the gate insulating layer over the PMOS active region and comprising a second metal gate electrode formed from the metal layer and having a second work function greater than the first work function.

10. The semiconductor device of claim 9, wherein the first work function ranges from between about 3.7 to 4.5 eV, and wherein the second work function ranges from between about 4.7 to 5.3 eV.

11. The semiconductor device of claim 10, wherein the metal layer comprises at least one of nickel (Ni), ruthenium oxide (RuO), molybdenum nitride (MoN), tantalum nitride (TaN), molybdenum silicide (MoSi₂), tantalum silicide (TaSi₂), and tantalum nitride (TaN).

12. The semiconductor device of claim 11, wherein the metal layer is formed using a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.

13. The semiconductor device of claim 9, wherein the NMOS and PMOS metal gate structures further comprise an additional conductive layer formed on the metal layer to define a profile height.

14. The semiconductor device of claim 13, wherein the metal layer is formed to a thickness of less than 100 Å

, and the additional conductive layer is formed to a thickness of greater than 1000 Å

.

15. The semiconductor device of claim 14, wherein the NMOS and PMOS metal gate structures comprise a stacked structure formed from a patterned portion of the additional conductive layer formed on a patterned portion of the metal layer formed on a patterned portion of the gate insulating layer, and gate spacers formed on sidewalls of the stacked structure.

16. The semiconductor device of claim 15, further comprising:

source and drain regions formed in the substrate on opposite sides of the NMOS and PMOS metal gate structures.

17. The semiconductor device, comprising:

NMOS and PMOS active regions formed in a substrate;

a gate insulating layer formed on the substrate over the NMOS and PMOS active regions;

a PMOS metal gate structure formed on the gate insulating layer over the PMOS active region and comprising a first metal gate electrode formed from a metal layer and doped with carbon to have a first work function; and

,

a NMOS metal gate structure formed on the gate insulating layer over the NMOS active region and comprising a second metal gate electrode formed from the metal layer and having a second work function less than the first work function.

18. The semiconductor device of claim 17, wherein the first work function ranges from between about 4.7 to 5.3 eV, and wherein the second work function ranges from between about 3.7 to 4.5 eV.

19. The semiconductor device of claim 18, wherein the metal layer comprises at least one of ruthenium (Ru), zirconium (Zr), niobium (Nb) and tantalum (Ta).

20. The semiconductor device of claim 19, wherein the metal layer is formed using a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.

21. The semiconductor device of claim 20, wherein the PMOS and NMOS metal gate structures further comprise an additional conductive layer formed on the metal layer to define a profile height.

22. The semiconductor device of claim 21, wherein the NMOS and PMOS metal gate structures comprise a stacked structure formed from a patterned portion of the additional conductive layer formed on a patterned portion of the metal layer formed on a patterned portion of the gate insulating layer, and gate spacers formed on sidewalls of the stacked structure.