Memory module and method having improved signal routing topology

• US 7,746,095 B2
• Filed: 06/08/2009
• Issued: 06/29/2010
• Est. Priority Date: 06/11/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Greeff, Roy E., Pax, George E.
• Primary Examiner(s): Mai; Lam T
• Application Number:
  US12/480,589
• Publication Number:
  US 20090243649A1
• Time in Patent Office: 386 Days
• Field of Search: 326 21- 30, 711/118, 711/170
• US Class Current: 326/21
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H05K 1/025 Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H01L23/66
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09254 Branched layout
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Claims

1. A memory module, comprising:

a plurality of memory devices;

a component having a plurality of input terminals and a plurality of output terminals; and

a symmetrical tree coupling each of several of the output terminals of the component to respective input terminals of the memory devices, the symmetrical tree comprising at least one branch, each branch including a pair of transmission lines coupled to each other at one end and to either a transmission line of another branch or one of the memory devices at another end, each of the transmission lines having a characteristic impedance, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having substantially the same characteristic impedance.

2. The memory module of claim 1, further comprising an initial transmission line coupling the component to one of the branches of the symmetrical tree.

3. The memory module of claim 2 wherein the initial transmission line is coupled only to either the component or to one of the branches of the symmetrical tree.

4. The memory module of claim 1 wherein each of the memory devices comprise a respective dynamic random access memory device.

5. The memory module of claim 1 wherein the component comprises an active memory component.

6. The memory module of claim 5 wherein the active memory component comprises a memory hub.

7. The memory module of claim 5 wherein the active memory component comprises a buffer.

8. The memory module of claim 1 wherein the transmission lines in each of the branches are configured so that respective propagation times during which a signal may propagate through the symmetrical tree from the component to each of the memory devices is substantially the same.

9. A module, comprising:

a plurality of first devices;

a second device; and

a symmetrical tree coupled to the second device, the symmetrical tree comprising a plurality of branches each of which comprises a pair of transmission lines coupled to each other and to another transmission line at one end and to either a transmission line of another branch or one of the first devices at another end, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having substantially the same length.

10. The module of claim 9, further comprising an initial transmission line having a first end coupled to the second device and a second end coupled to one of the branches of the symmetrical tree, the initial transmission line being coupled only to the second device and to the one of the branches.

11. The module of claim 9 wherein each of the first devices comprise a memory device, and wherein the second component comprises a memory hub.

12. The module of claim 9 wherein the second device comprises a buffer.

13. The module of claim 9, further comprising:

an third device; and

a dedicated transmission line coupling the second device to the third device.

14. The module of claim 13 wherein the dedicated transmission line is coupled only to the second device and the third device.

15. The module of claim 13 wherein the third device comprises a respective one of the second devices.

16. The memory module of claim 9 wherein both of the transmission lines in each of the hierarchies have the same length.

17. A module, comprising:

a plurality of first devices;

a second device; and

a symmetrical tree coupled to the second device, the symmetrical tree comprising at least one branch that comprises a pair of transmission lines coupled to each other and to another transmission line at one end and to either a transmission line of another branch or one of the first devices at another end, each of the transmission lines having a characteristic impedance, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having substantially the same characteristic impedance.

18. The module of claim 17 wherein each of the first devices comprise a memory device, and wherein the second device comprises a memory hub.

19. The module of claim 17 wherein each of the first devices comprise a memory device, and wherein the second device comprises a register for storing address and command signals and outputting the stored address and command signals to the memory devices.

20. The module of claim 17 wherein the characteristic impedance of each transmission line in each branch is approximately twice the characteristic impedance of any transmission line that it is connected between the transmission line and the second device.

21. The module of claim 17 wherein the second device is connected to one of the branches of the symmetrical tree through an initial transmission line, the initial transmission line having approximately half the characteristic impedance of the transmission lines in the branch to which it is connected.

22. The module of claim 17 wherein both of the transmission lines in each branch have substantially the same length.

23. A module, comprising:

a plurality of first devices;

a second device; and

a symmetrical tree coupled to the second device, the symmetrical tree comprising a plurality of branches each of which comprises a pair of transmission lines coupled to each other and to another transmission line at one end and to either a transmission line of another branch or one of the first devices at another end, the transmission lines being arranged in a plurality of hierarchies with both of transmission lines in the same hierarchy being configured so that a time period during which a signal may propagate through each of the transmission lines is substantially the same for both transmission lines.

24. the module of claim 23 wherein the transmission lines are configured so that respective propagation times during which a signal may propagate from the second device to each of the first devices is substantially the same.