Bus-based logic blocks for self-timed integrated circuits
First Claim
1. A bus-based logic block, comprising:
- N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another;
wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus;
N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another;
wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus; and
N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another.
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Abstract
A bus-based logic block in a self-timed integrated circuit includes N first input multiplexers, N second input multiplexers, and N lookup tables, N being greater than one. The select inputs of all N first input multiplexers are coupled together, and the select inputs of all N second input multiplexers are coupled together. A corresponding data input of each first input multiplexer is one bit of a first self-timed N-bit bus, and a corresponding data input of each second multiplexer is one bit of a second self-timed N-bit bus. Each lookup table has first and second inputs coupled to the outputs of the first and second input multiplexers. Corresponding control inputs of all N lookup tables are coupled together. Thus, all operations are performed on one or more N-bit self-timed busses, rather than on individual data signals.
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Citations
20 Claims
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1. A bus-based logic block, comprising:
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N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus; N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus; and N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit, comprising:
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an array of logic blocks; and an interconnect structure interconnecting the logic blocks, wherein each logic block comprises; N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus, the first self-timed N-bit bus being coupled to a first N-bit bus of the interconnect structure; N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus, the second self-timed N-bit bus being coupled to a second N-bit bus of the interconnect structure; and N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A programmable integrated circuit, comprising:
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an array of programmable logic blocks; and an interconnect structure interconnecting the programmable logic blocks, wherein each programmable logic block comprises; N first input multiplexers each having a select input, a plurality of data inputs, and an output, wherein N is an integer greater than one, wherein the select inputs of all N first input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N first input multiplexers comprises a corresponding bit of a first self-timed N-bit bus, the first self-timed N-bit bus being coupled to a first N-bit bus of the interconnect structure; N second input multiplexers each having a select input, a plurality of data inputs, and an output, wherein the select inputs of all N second input multiplexers are coupled one to another; wherein a corresponding one of the data inputs of each of the N second input multiplexers comprises a corresponding bit of a second self-timed N-bit bus, the second self-timed N-bit bus being coupled to a second N-bit bus of the interconnect structure; and N first lookup tables, each first lookup table having a first input coupled to the output of a corresponding one of the first input multiplexers, a second input coupled to the output of a corresponding one of the second input multiplexers, a plurality of control inputs, and an output, wherein corresponding control inputs of all N first lookup tables are coupled one to another. - View Dependent Claims (20)
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Specification