Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the same

• US 7,746,112 B1
• Filed: 04/02/2009
• Issued: 06/29/2010
• Est. Priority Date: 04/02/2009
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Young, Steven P., Gaide, Brian C.
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/417,043
• Time in Patent Office: 453 Days
• Field of Search: 326 37- 41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A cascading output structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes an array of interconnected logic blocks, each including a logic circuit, an output multiplexer, and a select multiplexer. The logic circuit has an input coupled to a logic block input. The output multiplexer has first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input, and an output coupled to a logic block output. The select multiplexer has a first data input coupled to a cascade select input of the logic block, a second data input, and an output coupled to the select input of the output multiplexer. The output of the select multiplexer is also coupled to a cascade select output of the logic block. The cascade select input of the logic block is coupled to the cascade select output of an adjacent logic block.

Claims

1. An integrated circuit, comprising:

an array of interconnected logic blocks, each of the logic blocks comprising;

a logic circuit having at least one input coupled to a an input of the logic block and further having first and second outputs;

a first output multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input, and an output coupled to a first output of the logic block; and

a select multiplexer having a first data input coupled to a cascade select input of the logic block, a second data input, and an output coupled to the select input of the first output multiplexer, the output of the select multiplexer being further coupled to a cascade select output of the logic block,

wherein the cascade select input of the logic block is coupled to the cascade select output of an adjacent logic block in the array.

2. The integrated circuit of claim 1, wherein each logic block further comprises an arbiter having inputs coupled to receive ready signals provided with the first and second outputs of the logic circuit, the arbiter further having an output coupled to the second data input of the select multiplexer.

3. The integrated circuit of claim 1, wherein each logic block further comprises a memory element coupled between the output of the select multiplexer and the select input of the first output multiplexer, and further coupled between the output of the select multiplexer and the cascade select output of the logic block.

4. The integrated circuit of claim 3, wherein in each logic block the memory element comprises a latch.

5. The integrated circuit of claim 1, wherein each logic block further comprises a second output multiplexer having first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the select multiplexer, and an output coupled to a second output of the logic block.

6. The integrated circuit of claim 1, wherein the logic blocks in the array are substantially similar one to another.

7. The integrated circuit of claim 1, wherein the integrated circuit comprises a programmable integrated circuit.

8. The integrated circuit of claim 7, wherein the programmable integrated circuit comprises a programmable logic device (PLD).

9. The integrated circuit of claim 6, wherein in each logic block the select multiplexer is programmable to select the cascade select input of the logic block as the output of the select multiplexer, wherein a cascade chain is formed such that a select signal applied to the first output multiplexer in a first of the logic blocks is cascaded through a column of the first output multiplexers in a subsequent plurality of the logic blocks.

10. An integrated circuit, comprising:

an interconnect structure;

a plurality of substantially similar logic circuits arrayed to form a column of the logic circuits, each of the logic circuits having at least one input coupled to the interconnect structure and further having first and second outputs; and

a vertical cascade chain having a plurality of first inputs coupled to the first outputs of the logic circuits, a plurality of second inputs coupled to the second outputs of the logic circuits, and a plurality of outputs coupled to the interconnect structure.

11. The integrated circuit of claim 10, wherein the cascade chain comprises:

a plurality of select multiplexers, each of the select multiplexers having first and second inputs, and further having an output coupled to an input of a subsequent select multiplexer in the vertical cascade chain; and

a plurality of first output multiplexers, each of the first output multiplexers having a first input coupled to one of the first inputs of the vertical cascade chain, a second input coupled to one of the second inputs of the vertical cascade chain, a select input coupled to the output of an associated one of the select multiplexers, and an output coupled to one of the outputs of the vertical cascade chain.

12. The integrated circuit of claim 11, wherein each of the select multiplexers is programmable to select one of an output from a preceding first select multiplexer or another input to place onto the cascade chain.

13. The integrated circuit of claim 11, wherein the cascade chain further comprises:

a plurality of second output multiplexers, each of the second output multiplexers having a first input coupled to one of the first inputs of the vertical cascade chain, a second input coupled to one of the second inputs of the vertical cascade chain, a select input coupled to the output of a corresponding one of the select multiplexers, and an output coupled to one of the outputs of the vertical cascade chain.

14. The integrated circuit of claim 10, wherein the integrated circuit comprises a programmable integrated circuit.

15. The integrated circuit of claim 14, wherein the programmable integrated circuit comprises a programmable logic device (PLD).

16. A method of placing data from a plurality of logic circuits onto an interconnect structure in a programmable integrated circuit, the method comprising:

programming each of the logic circuits to apply the data from the logic circuit to a corresponding data input of a corresponding first output multiplexer;

programmably coupling an initial select line to a data input of a first select multiplexer in a cascade chain of select multiplexers, each of the select multiplexers driving a select input of an associated first output multiplexer having an output coupled to the interconnect structure;

programming the first select multiplexer to pass a value on the initial select line to an output of the first select multiplexer; and

programming subsequent select multiplexers in the cascade chain to pass values received from preceding select multiplexers in the cascade chain to the outputs of the subsequent select multiplexers.

17. The method of claim 16, wherein each of the select multiplexers in the cascade chain further drives a select input of an associated second output multiplexer having an output coupled to the interconnect structure.

18. The method of claim 16, further comprising:

programming each of the first output multiplexers to select a polarity for each of the first output multiplexers.

19. The method of claim 18, wherein programming each of the first output multiplexers comprises storing configuration data into configuration memory cells coupled to the first output multiplexers.

20. The method of claim 16, wherein the programmable IC comprises a programmable logic device (PLD).