Bus switch and electronic switch

• US 7,746,114 B2
• Filed: 10/07/2008
• Issued: 06/29/2010
• Est. Priority Date: 11/14/2007
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Nagase, Kazuyoshi
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/285,476
• Publication Number:
  US 20090121776A1
• Time in Patent Office: 630 Days
• Field of Search: 326/26, 326/27, 326/82, 326/83, 327/333, 327/403, 327/427, 327/437
• US Class Current: 326/82
• CPC Class Codes: H04L 12/40182 by using a plurality of communication lines

Abstract

A bus switch for connecting and disconnecting a bus connection provided by a pair of buses includes a first switching element and a second switching element. The first switching element is coupled between an input terminal and an output terminal of a high-potential side bus of the pair of buses. The second switching element is coupled between an input terminal and an output terminal of a low-potential side bus of the pair of buses. The bus connection is connected when the first switching element and the second switching element are activated, and the bus connection is disconnected when the first switching element and the second switching element are deactivated.

Claims

1. A bus switch for connecting and disconnecting a bus connection that couples a plurality of nodes in a daisy chain manner, the bus connection provided by a pair of buses, a part of the plurality of nodes located on an upstream side of the bus switch and the other part of the plurality of nodes located on a downstream side of the bus switch, the bus switch comprising:

a supporting substrate;

a first switching element coupled between an input terminal and an output terminal of a high-potential side bus of the pair of buses;

a second switching element coupled between an input terminal and an output terminal of a low-potential side bus of the pair of buses, wherein;

the bus connection between the part of the plurality of nodes and the other part of the plurality of nodes is connected when the first switching element and the second switching element are activated;

the bus connection between the part of the plurality of nodes and the other part of the plurality of nodes is disconnected when the first switching element and the second switching element are deactivated;

each of the switching elements includes a plurality of metal-oxide semiconductor transistors and a plurality of resistor elements;

the plurality of metal-oxide semiconductor transistors are located on the supporting substrate and is coupled in series between the input terminal and the output terminal of corresponding one of the pair of buses so as to have a common source or a common drain;

each of the plurality of resistance elements is coupled between a source and a drain of a respective one of the plurality of metal-oxide semiconductor transistors;

each of the switching elements is activated when a predetermined electric current is supplied to the plurality of resistance elements; and

each of the switching elements is deactivated when the plurality of resistance elements is deenergized.

2. The bus switch according to claim 1, wherein

the plurality of metal-oxide semiconductor transistors is configured so that a plurality of parasitic diodes generated in the supporting substrate is coupled in series in such a manner that a conducting direction of one of the plurality of parasitic diodes is opposite to a conducting direction of another one of the plurality of parasitic diodes.

3. The bus switch according to claim 1, wherein

each of the switching elements is configured to apply a reverse bias to a plurality of parasitic diodes generated in the supporting substrate.

4. The bus switch according to claim 1, further comprising:

an electricity-supply circuit coupled between the high-potential side bus and the low-potential side bus, the electricity-supply circuit configured to supply the predetermined electric current to the plurality of the resistance elements so as to activate the first switching element and the second switching element; and

a current bypass circuit coupled between the high-potential side bus and the low-potential side bus, the current bypass circuit configure to divert the electric current that flows toward the plurality of resistance elements in the first switching element to the low-potential side bus.

5. The bus switch according to claim 1, further comprising:

a current source configured to supply the predetermined electric current to the plurality of resistance elements; and

a charge pump circuit configured to increase a potential of one or both of the high-potential side bus and the low-potential bus and configured to apply the increased potential to the current source.

6. The bus switch according to claim 1, wherein

each of the plurality of metal-oxide semiconductor transistors is an n-channel metal-oxide semiconductor transistor.

7. The bus switch according to claim 1, wherein:

the supporting substrate has a silicon on insulator structure including a silicon substrate and an insulating layer disposed on the silicon substrate;

the supporting substrate further has an element forming region on the silicon on insulator structure; and

the plurality of metal-oxide semiconductor transistors is located in the element forming region.

8. The bus switch according to claim 1, wherein a configuration of a circuit coupled to the high-potential side bus and a configuration of a circuit coupled to the low-potential side bus have a symmetry.

9. An electronic switch comprising;

an input terminal;

an output terminal; and

a switching element coupled between the input terminal and the output terminal, wherein;

the switching element includes a supporting substrate, a plurality of metal-oxide semiconductor transistors, and a plurality of resistance elements;

the plurality of metal-oxide semiconductor transistors is located on the supporting substrate and is coupled in series between the input terminal and the output terminal so as to have a common source or a common drain;

each of the plurality of resistance elements is coupled between a gate and a source of a respective one of the plurality of metal-oxide semiconductor transistors;

the switching element is activated when a predetermined electric current is supplied to the plurality of resistance elements; and

the switching element is deactivated when the plurality of resistance elements is deenergized.

10. The electronic switch according to claim 9, wherein

the plurality of metal-oxide semiconductor transistors is configured so that a plurality of parasitic diodes generated in the supporting substrate is coupled in series in such a manner that a conducting direction of one of the plurality of parasitic diodes is opposite to a conducting direction of another one of the plurality of parasitic diodes.

11. The electronic switch according to claim 9, wherein

the switching element is configured to apply a reverse bias to a plurality of parasitic diodes generated in the supporting substrate.

12. The electronic switch according to claim 9, further comprising

a recovering unit configured to recover the electric current that flows toward the plurality of resistance elements.

13. The electronic switch according to claim 9, wherein

each of metal-oxide semiconductor transistors is an n-channel metal-oxide semiconductor transistor.

14. The electronic switch according to claim 9, wherein:

the supporting substrate has a silicon on insulator structure including a silicon substrate and an insulating layer disposed on the silicon substrate;

the supporting substrate further has an element forming region on the silicon on insulator structure; and

the plurality of metal-oxide semiconductor transistors is located in the element forming region.

15. The electronic switch according to claim 9, further comprising:

another input terminal;

another output terminal; and

another switching element coupled between the another input terminal and the another output terminal, wherein

a configuration of a circuit coupled between the input terminal and the output terminal and a configuration of a circuit coupled between the another input terminal and the another output terminal have a symmetry.