Sub-micron high input voltage tolerant input output (I/O) circuit

• US 7,746,124 B2
• Filed: 05/15/2009
• Issued: 06/29/2010
• Est. Priority Date: 01/09/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ajit, Janardhanan S.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US12/467,002
• Publication Number:
  US 20090224821A1
• Time in Patent Office: 410 Days
• Field of Search: None
• US Class Current: 327/108
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Claims

1. An apparatus for generating a bias voltage at a bias node, the apparatus comprising:

a first input configured to accept a pad voltage from an input/output (I/O) circuit;

a second input configured to accept an output enable signal;

a third input configured to accept a first input voltage;

a fourth input configured to accept a second input voltage; and

a bias circuit configured to provide the first input voltage to the bias node when the pad voltage is equal to the second input voltage when the output enable signal is at a disable value and to provide a voltage depending on the pad voltage to the bias node when the pad voltage is greater than the second input voltage when the output enable signal is at the disable value.

2. The apparatus of claim 1, wherein the voltage depending on the pad voltage is an increasing voltage tracking the pad voltage.

3. The apparatus of claim 1, further comprising:

a transistor coupled to the bias node, the bias circuit ensuring that the transistor is operating in a safe range to prevent damage to a junction of the transistor.

4. The apparatus of claim 3, wherein the transistor is a P-channel Metal Oxide Semiconductor (PMOS).

5. The apparatus of claim 1, wherein the I/O circuit is configurable to operate in an input mode or an output mode in response to the output enable signal.

6. The apparatus of claim 5, wherein the I/O circuit is configured to operate in the input mode when the output enable signal corresponds to the disable value.

7. The apparatus of claim 5, wherein the I/O circuit is configured to operate in the output mode when the output enable signal corresponds to an enable value.

8. An apparatus for generating a bias voltage at a bias node, the apparatus comprising:

an input/output (I/O) circuit configured to operate in an input mode or an output mode in response to an output enable signal, to send a first signal to a device in the output mode, and to receive a second signal from the device in the input mode, the first signal and second signal being characterized by a pad voltage on the I/O circuit; and

a bias circuit configured to provide a first voltage to the bias node when the pad voltage is equal to an input voltage when the I/O circuit is operating in the input mode and to provide a second voltage depending on the pad voltage to the bias node when the pad voltage is greater than the input voltage when the I/O circuit is operating in the input mode.

9. The apparatus of claim 8, further comprising:

a transistor coupled to the bias node, configured to ensure that the transistor is operating in a safe range to prevent damage to a junction of the transistor.

10. The apparatus of claim 8, wherein the second voltage depending on the pad voltage is an increasing voltage tracking the pad voltage.

11. The apparatus of claim 8, further comprising:

a transistor, coupled to the bias node, configured to divide the pad voltage in response the bias node.