Junction field effect transistor input buffer level shifting circuit

• US 7,746,146 B2
• Filed: 09/01/2006
• Issued: 06/29/2010
• Est. Priority Date: 07/28/2006
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Thummalapally, Damodar R., Chou, Richard K.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US11/515,252
• Publication Number:
  US 20080042723A1
• Time in Patent Office: 1,397 Days
• Field of Search: 327/306, 327/333, 326 62- 63, 326 80- 81
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356034 the input circuit having a differential configuration

Abstract

A level shifting circuit can include a first input junction field effect transistor (JFET) having a gate coupled to receive an input signal having a first voltage swing that provides a controllable impedance path between a first supply node and a first terminal of a first bias stack including at least one JFET. A driver circuit can be coupled to receive an output from the first bias stack that provides a level shifted output having a second voltage swing that is less than the first voltage swing.

Claims

1. A method of interfacing between a first semiconductor device including junction field effect transistors (JFETs) and a bus, comprising the steps of:

receiving an input signal having a first voltage swing at an input terminal of the first semiconductor device including JFETs;

translating the input signal to an internal signal having a second voltage swing lower than the first voltage swing;

providing the input signal onto the bus from a second semiconductor device operating at a second power supply voltage higher than a first power supply voltage at which the first semiconductor device operates;

receiving the internal signal by core circuitry including JFETs and operating at a first power supply voltage;

providing a second internal signal having essentially the second voltage swing from the core circuitry; and

translating the second internal signal to an output signal having essentially the first voltage swing.

2. The method of claim 1, wherein:

the first voltage swing is substantially greater than the second voltage swing.

3. The method of claim 1, wherein:

the first power supply voltage is essentially the same value as the second voltage swing.

4. The method of claim 1, wherein:

the second voltage swing is about 0.5 volts.

5. The method of claim 1, further including:

providing the input signal onto the bus from a second semiconductor device operating at a second power supply voltage higher than a first power supply voltage at which the first semiconductor device operates.

6. A system, comprising:

at least a first semiconductor device, comprising

an input buffer including at least one junction field effect transistor (JFET), the input buffer receiving an input signal having a first voltage swing and providing a shifted signal having a second voltage swing lower than the first voltage swing; and

core circuitry comprising JFETs, the core circuitry coupled to receive the shifted signal wherein the core circuitry operates from a first power supply having a magnitude less than the first voltage swing; and

an output buffer including at least one JFET, the output buffer coupled to receive a first signal having essentially the second voltage swing from the core circuitry and providing an output signal having essentially the first voltage swing.

7. The semiconductor device of claim 6, wherein:

the first semiconductor device further includes a higher voltage section coupled to and formed in the same substrate as the output buffer, the higher voltage section operating at a power supply level greater than the first power supply.

8. The semiconductor device of claim 7, wherein:

the higher voltage section comprises insulated gate field effect transistors (IGFETs).

9. The system of claim 6, further including:

at least a second semiconductor device coupled to the output buffer of the first semiconductor device by at least one signal line, the second semiconductor device operating at a power supply level greater than the first power supply.

10. The system of claim 6, further including:

the first power supply has a magnitude of less than a forward bias voltage of a pn junction formed by at least one of the JFETs in the core circuitry and the core circuitry includes complementary JFETs.

11. The system of claim 6, further including:

at least a second semiconductor device coupled to the input buffer of the first semiconductor device by at least one signal line, the second semiconductor device operating at a power supply level greater than the first power supply.

12. The semiconductor device of claim 6, wherein:

the first semiconductor device further includes a higher voltage section formed in the same substrate as the input buffer circuit and coupled thereto, the higher voltage section operating at a power supply level greater than the first power supply.

13. The semiconductor device of claim 11, wherein:

the higher voltage section comprises insulated gate field effect transistors (IGFETs).