Beam-former and combiner for a multiple-antenna system

• US 7,746,967 B2
• Filed: 04/30/2003
• Issued: 06/29/2010
• Est. Priority Date: 04/30/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ho, Minnie, Sandhu, Sumeet
• Primary Examiner(s): Bocure; Tesfaldet
• Application Number:
  US10/427,187
• Publication Number:
  US 20040219899A1
• Time in Patent Office: 2,617 Days
• Field of Search: 375/346, 375/347, 375/348, 375/349, 375/316, 375/219, 375/267, 375/299, 375/345, 375/295, 375/296, 455/91, 455/132, 455/101, 455136-139, 455/232.1, 455/234.1, 455/237.1, 455/239.1, 455/240.1
• US Class Current: 375/347
• CPC Class Codes: H04B 7/0842 Weighted combining
• CPC Class Codes: H04B 7/0851 using training sequences or error signal minimizing error signal H04B7/0854
• CPC Class Codes: H04B 7/0854 using error minimizing algorithms, e.g. minimum mean squared error [MMSE], "cross-correlation" or matrix inversion

Abstract

A compensating correction value for adjusting analog signals received from multiple antenna elements takes into account the effects of colored noise, co-channel interference, and inter-sample interference. The method of generating the compensating correction value for analog combining architectures considers the total channel impulse response over a block of time.

Claims

1. A system comprising:

a Static Random Access Memory (SRAM);

a communication processor coupled via an external bus to the SRAM, where the communication processor receives modulated signals at multiple antenna and computes a compensating correction value for analog signals from multiple antenna elements, wherein the compensating correction value is derived from known symbols sent over a network to the receiver that corresponds to each antenna element;

an amplifier circuit coupled to a phase shifter to receive the modulated signals; and

a Digital-To-Analog Converter (DAC) coupled to the communication processor to receive the compensating correction value and adjust a gain of the amplifier circuit and a phase in the phase shifter of the received modulated signals.

2. The system of claim 1, wherein the compensating correction value is determined for a channel in the time-domain or in the frequency-domain as selected by the system.

3. The system of claim 1, wherein the communication processor processes quadrature signals from a receiver chain to provide the compensating correction value to the DAC to mitigate effects of channel multi-path.

4. The system of claim 1, wherein the communication processor processes quadrature signals from first and second receiver chains to mitigate effects of Inter-Symbol Interference (ISI).

5. The system of claim 1, wherein the communication processor processes quadrature signals for a linear combiner in a receiver and a beamformer in a transmitter.

6. The system of claim 5, further including:

a transmitter having an amplifier and a power amplifier; and

a DAC coupled to the amplifier and the power amplifier to phase shift and amplify signals prior to transmission using the compensating correction value for the beam-former.