Method for controlling a memory access

• US 7,747,832 B2
• Filed: 12/22/2004
• Issued: 06/29/2010
• Est. Priority Date: 12/22/2003
• Status: Active Grant

• Current Assignee: Micranos GmbH
• Original Assignee: Micronas Gmbh (TDK Corporation)
• Inventors: Franke, Joerg
• Primary Examiner(s): Chace; Christian P
• Assistant Examiner(s): RUTZ, JARED IAN
• Application Number:
  US11/020,880
• Publication Number:
  US 20050160246A1
• Time in Patent Office: 2,015 Days
• Field of Search: 711/104, 711/167, 710/17
• US Class Current: 711/167
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

The invention relates to a method and a corresponding device for controlling a memory access, wherein a number of waiting states is established for the memory access to a storage device (FLASH/ROM, RAM, IO module) for a central control unit (CPU). A memory access is made possible in that the number of waiting states for the memory access is established individually as a function of an analysis of an instantaneous state (status) of the central control unit (CPU) and/or a type and/or address of the storage device (FLASH/ROM, RAM, IO module) being accessed.

Claims

1. A method for controlling a memory access to a storage device, comprising the steps of:

determining a number of waiting states for the memory access to the storage device by a central control unit, where the step of determining further comprises the step of analyzing at least one of a current state of the central control unit, a type of the storage device being accessed, and an address of the storage device being accessed; and

comparing in an address comparator an address at a current point in time with an address at an earlier point in time to determine whether the current address is assigned to a storage device without required waiting states and to determine whether the current address prior to the current address and subsequent to the current address is assigned to a storage device with required waiting states, where the number of required waiting states for memory access with required waiting states is reduced if the memory accesses to the storage device with required waiting states involve one of incrementing addresses, same addresses, or addresses of the same memory page.

2. The method of claim 1, further comprising the steps of where the memory control unit in the cycle of the memory access to the storage device generates an additional address and provides the additional address to the storage device.

3. A method for controlling a memory access to an storage device, comprising the steps of:

determining a number of waiting states for the memory access to the storage device by a control unit, where the step of determining further comprises the step of analyzing at least one of a current state of the control unit, a type of the storage device being accessed, and an address of the storage device being accessed; and

comparing an address at a current point in time with an address at an earlier point in time to determine whether the current address is assigned to a storage device without required waiting states and to determine whether the current address prior to the current address and subsequent to the current address is assigned to a storage device with required waiting states, where the number of required waiting states for memory access with required waiting states is reduced if the memory accesses to the storage device with required waiting states involve one of incrementing addresses, same addresses, or addresses of the same memory page.