Dual ported replicated data cache

• US 7,747,896 B1
• Filed: 06/30/2006
• Issued: 06/29/2010
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Klaiber, Alex, Rozas, Guillermo, Masleid, Robert P.
• Primary Examiner(s): Baker; Stephen M
• Application Number:
  US11/479,630
• Time in Patent Office: 1,460 Days
• Field of Search: 714/6, 714/805
• US Class Current: 714/6.12
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 12/0853 Cache with multiport tag or data arrays

Abstract

A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.

Claims

1. A method for storing a small data block in a cache system, comprising:

augmenting the small data block with error detection information to produce an augmented data block;

storing the augmented data block in a first memory array;

storing the augmented data block in second memory array;

retrieving the augmented data block from one of the first memory array and the second memory array; and

if there is a bit error in the retrieved augmented data block, evicting the augmented data block.

2. The method of claim 1, wherein the evicting comprises:

reading a first cache line from the first memory array comprising the augmented data block;

reading a second cache line from the second memory array comprising the augmented data block; and

generating a small data block of the cache line from a corresponding error-free small data block of the first cache line and the second cache line.

3. The method of claim 1, where the cache system is a write-back cache.

4. The method of claim 1, where the cache system is dual-ported.

5. The method of claim 1, further comprising:

retrieving the augmented data block from the first memory array; and

if there is a bit error in the retrieved augmented data block, retrieving and delivering the augmented data block from the second memory array.

6. The method of claim 5, where retrieving the augmented data block from the second memory array comprises:

reading the augmented data block from the second memory array; and

writing the augmented data block retrieved from the second memory array to the first memory array.

7. The method of claim 1, where the first memory array is comprised of single port memory cells.

8. The method of claim 7, where the single port memory cells are SRAM.

9. The method of claim 1, where the cache system is a write-back cache.

10. The method of claim 9, where the cache system is dual-ported.

11. A cache system for storing an input data block, comprising:

an augmenter producing an augmented data block with parity information from the input data block;

a first memory array storing the augmented data block;

a second memory array storing the augmented data block;

an error detector that produces an error signal if the augmented data block retrieved from the first memory array has a bit error; and

a retrieval means for retrieving the augmented data block from the second memory array upon receiving the error signal and for evicting the cache line containing the augmented data block.

12. The cache system of claim 11, where said cache system is a write-back cache.

13. The cache system of claim 11, where said cache system has more than one access port.

14. The cache system of claim 11, where the input data block size is no more than 16 bits.

15. The cache system of claim 11, wherein the retrieval means comprises means for evicting the cache line containing the augmented data block.

16. The cache system of claim 11, where said first memory array is comprised of single port memory cells.

17. The cache system of claim 16, where the single port memory cells are SRAM.

18. A dual ported cache system, comprising:

a first single ported cache;

a second single ported cache,

a first load port coupled to the first single ported cache; and

a second load port coupled to the second single ported cache, wherein the first single ported cache is configured to store data and the second single ported cache is configured to store a copy of the data, wherein the data and the copy of the data are accessed via the first load port and the second load port respectively;

a first error detector coupled to the first single ported cache; and

a second error detector coupled to the second single ported cache, wherein the first and second detectors are configured to detect an error in a data block retrieved from one of the first single ported cache and the second single ported cache.

19. The cache system of claim 18, wherein the first load port and the second load port are configured to provide independent access to the first single ported cache and the second single ported cache.

20. The cache system of claim 18, further comprising:

a first memory unit coupled to the first load port; and

a second memory unit coupled to the second load port, wherein the first memory unit and the second memory unit are located substantially adjacent to the first load port and the second load port respectively.

21. The cache system of claim 18, wherein the cache system is a write through cache system.

22. The cache system of claim 18, wherein the cache system is a write-back cache system.

23. The cache system of claim 18, further comprising

a crossbar coupled to access either the data block or a copy of the data block which is error-free.

24. The cache system of claim 18, wherein the first single ported cache and the second single ported cache comprise independent memory arrays.

25. The cache system of claim 24, wherein the independent memory arrays are fabricated utilizing a common SRAM cell.