BIST scan path parts with test generator and compactor circuitry

• US 7,747,919 B2
• Filed: 03/18/2009
• Issued: 06/29/2010
• Est. Priority Date: 03/09/2000
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US12/406,348
• Publication Number:
  US 20090183042A1
• Time in Patent Office: 468 Days
• Field of Search: 714/724, 714/726, 714/727, 714/729
• US Class Current: 714/729
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318575 Power distribution; Power saving

Abstract

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Claims

1. A scan BIST circuit within an integrated circuit, comprising:

A. scan path circuitry having plural scan path parts, each part having a separate scan input, scan output, clock input and enable input;

B. test pattern generator circuitry having a control input and a stimulus data output, the stimulus data output being coupled with the scan input of each scan path part;

C. compactor circuitry having a control input and a response data input, the response data input being selectively coupled with the scan output of each scan path part;

D. controller circuitry having a clock output, an enable output, a control output coupled to the control input of the test pattern generator circuitry, and a control output coupled to the control input of the compactor circuitry; and

E. adapter circuitry having a clock input and an enable input coupled with the respective clock output and enable output of the controller circuitry, and having a separate clock output and an enable output coupled with the separate clock input and enable input of each scan path part.

2. The circuit of claim 1 in which the scan path circuitry includes scan cells, each scan cell includes a multiplexer and a flip-flop with an output of the multiplexer being an input to the flip-flop, the multiplexer having response data and scan data inputs and the flip-flop having an output providing stimulus data and scan data.

3. The circuit of claim 1 in which the scan path circuitry includes scan cells, each scan cell includes a multiplexer and a flip-flop with an output of the multiplexer being an input to the flip-flop, the multiplexer having response data and scan data inputs and the flip-flop having an output providing stimulus data and scan data, the multiplexer having a scan enable control input connected to the enable signal input of a scan path part and the flip-flop having a clock input connected to the clock signal input of the scan path part.

4. The circuit of claim 1 including functional circuitry coupled to the scan path circuitry to receive stimulus data from the scan path circuitry and to return response data to the scan path circuitry.