Method and device for securing the reading of a memory

• US 7,747,935 B2
• Filed: 12/12/2007
• Issued: 06/29/2010
• Est. Priority Date: 12/18/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Berard, Nicolas, Bancel, Frederic, Hely, David
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US11/954,606
• Publication Number:
  US 20080228989A1
• Time in Patent Office: 930 Days
• Field of Search: None
• US Class Current: 714/819
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

A method reads a datum saved in a memory by selecting an address of the memory in which the datum to be read is saved, reading the datum in the memory at the selected address, saving the datum read in a storage space, and when the memory is not being accessed by a CPU, reading the datum in the memory, reading the datum saved in the storage space, and activating an error signal if the datum read in the memory is different from the datum saved. The method can be applied particularly to the protection of smart card integrated circuits.

Claims

1. A method, comprising:

selecting an address indicating a storage location of a memory;

reading a first datum from the storage location indicated by the selected address;

saving in a first storage space the first datum read from the storage location;

saving in a second storage space, associated with the first storage space, the selected address;

accessing the selected address from the second storage space;

reading a second datum from the storage location of the memory using the selected address accessed from the second storage space;

reading from the first storage space the first datum saved in the first storage space; and

activating an error signal if the second datum read from the memory is different from the first datum saved in the first storage space.

2. The method according to claim 1, further comprising saving in the first storage space several data read at consecutive addresses in the memory, the several data being saved in the first storage space in association with a single address and a number corresponding to the number of data saved in association with the single address.

3. The method according to claim 1, further comprising:

reading data at addresses in the memory; and

saving the data in the first storage space, wherein the data saved in the first storage space are checked according to a random order.

4. The method according to claim 1, further comprising:

reading data at addresses in the memory; and

saving the data randomly in the first storage space.

5. The method according to claim 1, comprising:

reading data at addresses in the memory;

saving the data in the first storage space;

determining that the first storage space is full; and

interrupting the reading of the memory in response to determining that the first storage space is full, and checking whether the data saved in the first storage space are identical to the corresponding data in the memory.

6. The method according to claim 5, wherein the interrupting step includes either blocking a clock signal pacing a central processing unit accessing the memory, or triggering the central processing unit to execute a waiting routine stored in another memory.

7. The method according to claim 1, wherein the reading the datum at the selected address is performed in response to a read request from a central processing unit and the reading the datum from the memory is performed while the central processing unit is not accessing the memory.

8. A device for protecting the reading of a memory, comprising:

a storage space configured to save a first datum read from a storage location in the memory identified by a selected address, and save the selected address in association with the first datum;

means for reading a second datum from the memory by using the saved selected address;

a comparator configured to compare the first datum saved in the storage space with the second datum read from the memory; and

means for activating an error signal if the first datum saved is different from the second datum read from the memory.

9. The device according to claim 8, wherein the storage space is configured to store data from the memory, and for each datum saved, the address of the datum in the memory.

10. The device according to claim 8, wherein the storage space is configured to store a single address for a set of saved data located at consecutive addresses in the memory, and a number corresponding to the number of data in the set of data.

11. The device according to claim 8, wherein the storage space is configured to store data from the memory, and wherein the data are saved in the storage space in a stack managed in FIFO or LIFO mode.

12. The device according to claim 8, wherein the storage space is configured to store data from the memory and addresses respectively corresponding to the data, wherein the addresses are saved in the storage space in a stack managed in FIFO or LIFO mode.

13. The device according to claim 8, wherein the memory to be protected is integrated with the storage space, means for reading, comparator, and means for activating.

14. An integrated circuit, comprising:

a central processing unit;

a memory read by the central processing unit;

a protection device that includes;

a storage space configured to save each datum read from the memory by the central processing unit;

means for checking, while the central processing unit is not accessing the memory, the data saved in the storage space, the checking including re-reading the data from the memory, comparing each datum saved in the storage space with a corresponding datum re-read from the memory, and activating an error signal if the datum saved is different from the datum re-read from the memory.

15. The integrated circuit according to claim 14, wherein the protection device comprises a multiplexer having a first input coupled to an address bus of the central processing unit, a second input coupled to the storage space, and an output coupled to an address bus of the memory, the multiplexer being structured to apply to the memory a read address coming either from the central processing unit, or from the storage space.

16. The integrated circuit according to claim 14, wherein the protection device comprises means for controlling the reading of the memory while the central processing unit is not accessing the memory.

17. The integrated circuit according to claim 14, wherein the protection device includes a sequencer having an input coupled to the central processing unit to receive a control signal whenever the central processing unit requests to read from the memory, the sequencer having an output coupled to the storage space and being configured to control writing to the storage space in response to receiving the control signal from the central processing unit

18. The integrated circuit according to claim 14, wherein the storage space is configured to save a first datum read from a storage location in the memory identified by a selected address, and save the selected address in association with the first datum and the means for checking includes:

means for reading a second datum from the memory by using the saved selected address;

a comparator configured to compare the first datum saved in the storage space with the second datum read from the memory; and

means for activating the error signal if the first datum saved is different from the second datum read from the memory.