Back-illuminated imager and method for making electrical and optical connections to same

• US 7,749,799 B2
• Filed: 11/15/2006
• Issued: 07/06/2010
• Est. Priority Date: 11/15/2005
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Pain, Bedabrata
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): NEWTON, VALERIE N
• Application Number:
  US11/600,583
• Publication Number:
  US 20070117254A1
• Time in Patent Office: 1,329 Days
• Field of Search: 438/60, 438 65- 70
• US Class Current: 438/75
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing

Abstract

Methods for bringing or exposing metal pads or traces to the backside of a backside-illuminated imager allow the pads or traces to reside on the illumination side for electrical connection. These methods provide a solution to a key packaging problem for backside thinned imagers. The methods also provide alignment marks for integrating color filters and microlenses to the imager pixels residing on the frontside of the wafer, enabling high performance multispectral and high sensitivity imagers, including those with extremely small pixel pitch. In addition, the methods incorporate a passivation layer for protection of devices against external contamination, and allow interface trap density reduction via thermal annealing. Backside-illuminated imagers with illumination side electrical connections are also disclosed.

Claims

1. A method of fabricating a backside-illuminated imaging structure, comprising:

providing a wafer having a frontside and a backside;

forming a device layer including one or more imager structures on the frontside of the wafer;

forming a metal and dielectric stack on the device layer;

providing electrical access from the backside of the wafer to the metal and dielectric stack;

providing one or more first alignment marks or features on the frontside of the wafer in respective one or more first positions; and

providing one or more second alignment marks or features on the backside of the wafer in respective one or more second positions different from the one or more first positions by using the one or more first alignment marks or features as a positioning guide for the second one or more alignment marks or features.

2. The method according to claim 1 further comprising deposition of a passivation layer on at least part of the backside of the wafer.

3. The method according to claim 1 further comprising heating the backside-illuminated imaging structure in an appropriate environment for passivation of interface traps and improving device performance.

4. The method according to claim 1 further comprising supporting the wafer on the frontside with a backing substrate.

5. The method according to claim 4 wherein the backing substrate is attached to the metal and dielectric stack.

6. The method according to claim 1 further comprising providing at least one of a color filter array and a microlens array on the backside of the wafer.

7. The method according to claim 1 further comprising providing at least one of a color filter array and a microlens array on the backside of the wafer and wherein the second alignment marks or features are used to align at least one of a color filter array and a microlens array so that at least one imager structure is optically aligned with at least one of a color filter and a microlens.

8. The method according to claim 1 further comprising one or more pads of conductive material on the backside of the wafer, at least one of the pads being in electrical connection to the backside of the wafer.

9. The method according to claim 8 wherein the one or more second alignment marks or devices comprise the one or more pads of conductive material.

10. The method according to claim 1 wherein the step of providing electrical access from the metal and dielectric stack to the backside of the wafer comprises forming a at least one cavity in the wafer between the metal and dielectric stack and the backside, providing one or more alignment marks in connection with the cavity, electrically isolating the cavity from the wafer, filling the cavity with a conductive material, and adding a conductive pad on the backside of the wafer in electrical communication with the conductive material.

11. The method according to claim 10 wherein more than one cavity is formed in the wafer between the metal and dielectric stack and the backside and each cavity is electrically isolated from each other as well as from the wafer.

12. The method according to claim 10 wherein the step of electrically isolating the cavity from the wafer comprises providing the cavity with a dielectric liner.

13. The method according to claim 10 wherein the cavity is formed by making a larger cavity opening on the frontside of the wafer and lining the larger cavity with a dielectric liner and further comprising providing one or more microcavities projecting from the cavity adjacent the backside of the wafer, wherein the cavity and the one or more projecting microcavities are filled with the conductive material, the filled one or more microcavities form one or more second alignment marks and are visible on the backside of the wafer, wherein the one or more second alignment marks are used to align the conductive pad.

14. The method according to claim 10 further comprising forming a larger cavity opening on the frontside of the wafer and filling the larger cavity with a dielectric and the one or more alignment marks are provided in the metal and dielectric stack, and further comprising forming the cavity in the dielectric from the backside in the dielectric and filling the second cavity with the conductive material.

15. The method according to claim 1 wherein the step of providing electrical access from the metal and dielectric stack to the backside of the wafer comprises forming at least one cavity in the wafer between the metal and dielectric stack and the backside to expose one or more metal traces in the metal and dielectric stack.

16. The method according to claim 15 wherein the cavity is formed in one or more stages.

17. The method according to claim 15 further comprising dicing the wafer at the cavity and expose the one or more metal traces to a side of the wafer formed by the dicing.

18. A method of fabricating a backside-illuminated imaging structure, comprising:

providing a wafer having a frontside and a backside;

forming a device layer including one or more imager structures on the frontside of the wafer;

forming a metal and dielectric stack on the device layer;

providing electrical access from the backside of the wafer to the metal and dielectric stack; and

providing one or more first alignment marks or features on the frontside of the wafer,

wherein providing electrical access from the metal and dielectric stack to the backside of the wafer comprises forming a at least one cavity in the wafer between the metal and dielectric stack and the backside, providing one or more alignment marks in connection with the cavity, electrically isolating the cavity from the wafer, filling the cavity with a conductive material, and adding a conductive pad on the backside of the wafer in electrical communication with the conductive material, and

wherein the cavity is formed by making a larger cavity opening on the frontside of the wafer and lining the larger cavity with a dielectric liner and further comprising providing one or more microcavities projecting from the cavity adjacent the backside of the wafer, wherein the cavity and the one or more projecting microcavities are filled with the conductive material, the filled one or more microcavities form one or more second alignment marks and are visible on the backside of the wafer, wherein the one or more second alignment marks are used to align the conductive pad.

19. A method of fabricating a backside-illuminated imaging structure, comprising:

providing a wafer having a frontside and a backside;

forming a device layer including one or more imager structures on the frontside of the wafer;

forming a metal and dielectric stack on the device layer;

providing electrical access from the backside of the wafer to the metal and dielectric stack; and

providing one or more first alignment marks or features on the frontside of the wafer,

wherein providing electrical access from the metal and dielectric stack to the backside of the wafer comprises forming a at least one cavity in the wafer between the metal and dielectric stack and the backside, providing one or more alignment marks in connection with the cavity, electrically isolating the cavity from the wafer, filling the cavity with a conductive material, and adding a conductive pad on the backside of the wafer in electrical communication with the conductive material,

the method further comprising forming a larger cavity opening on the frontside of the wafer and filling the larger cavity with a dielectric and the one or more alignment marks are provided in the metal and dielectric stack, and further comprising forming the cavity in the dielectric from the backside in the dielectric and filling the second cavity with the conductive material.