Thin film transistor array panel and manufacturing method thereof

• US 7,749,824 B2
• Filed: 07/27/2005
• Issued: 07/06/2010
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Primary Examiner(s): Such; Matthew W
• Application Number:
  US11/192,208
• Publication Number:
  US 20060024895A1
• Time in Patent Office: 1,805 Days
• Field of Search: 438149-166, 349 42- 43, 257/E21.023, 257/E21.411, 257/E21.412, 257/E21.414
• US Class Current: 438/158
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact on the semiconductor layer; forming a data line and a drain electrode on the ohmic contact; depositing a passivation layer on the data line and the drain electrode; forming a first photoresist layer on the passivation layer; etching the passivation layer and the gate insulating layer using the first photoresist layer as a mask to expose a portion of the drain electrode and a portion of the substrate; depositing a conductive film; and removing the photoresist layer; to form a pixel electrode on a portion of the drain electrode exposed by the etching of the passivation layer.

Claims

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming an ohmic contact layer on the semiconductor layer;

forming a data line and a drain electrode on the ohmic contact layer;

depositing a passivation layer on the data line and the drain electrode;

forming a first photoresist layer on the passivation layer, wherein the first photoresist layer does not cover at least a portion of the passivation layer and the gate insulating layer;

etching the passivation layer and the gate insulating layer which are not covered by the first photoresist layer;

exposing a portion of the substrate;

transforming the first photoresist layer into a second photoresist layer, wherein the second photoresist layer does not cover at least a portion of the passivation layer;

etching the passivation layer which is not covered by the second photoresist layer;

exposing a portion of the drain electrode;

depositing a conductive film on the drain electrode and on the second photoresist layer, the conductive film including a first portion disposed on the second photoresist layer and a second portion at least partially separated from the first portion by gaps, the gaps exposing at least a portion of lateral sides of the second photoresist layer;

removing the second photoresist layer and the first portion of the conductive film; and

forming a pixel electrode on the portion of the drain electrode.

2. The method of claim 1, wherein forming the first photoresist layer further comprises using a photo mask including a light blocking area, a translucent area, and a light transmitting area.

3. The method of claim 1, wherein the transforming of the first photoresist layer into the second photoresist layer comprises ashing.

4. The method of claim 1, wherein:

the second portion is disposed directly on the substrate; and

the removing of the second photoresist layer further includes removing the first portion of the conductive film by lift off.

5. The method of claim 1, wherein the conductive film directly contacts the substrate and the gate insulating layer.

6. The method of claim 1, wherein:

the etching of a portion of the passivation layer which is not covered by the second photoresist layer further comprises;

exposing a portion of the data line; and

the removing of the second photoresist layer further comprises;

forming a contact assistant on the exposed portion of the data line.

7. The method of claim 1, wherein the forming of the gate insulating layer, the forming of the semiconductor layer, the forming of the ohmic contact layer, and the forming of the data line and the drain electrode comprises:

sequentially depositing the gate insulating layer, an intrinsic amorphous silicon layer, an extrinsic amorphous silicon layer, and a data conductor layer;

forming a third photoresist layer on the data conductor layer, wherein the third photoresist layer does not cover at least a portion of the data conductor layer, the extrinsic amorphous silicon layer, and the intrinsic amorphous silicon layer;

sequentially etching portions of the data conductor layer, the extrinsic amorphous silicon layer, and the intrinsic amorphous silicon layer which are not covered by the third photoresist layer;

forming a data conductor, an ohmic contact layer, and a semiconductor layer;

partially removing the third photoresist layer;

forming a fourth photoresist layer;

etching the data conductor and the ohmic contact layer; and

forming the data line, the drain electrode, and the ohmic contact layer.

8. The method of claim 7, wherein forming the third photoresist layer further comprises using a photo mask including a light blocking area, a translucent area, and a light transmitting area.

9. The method of claim 7, wherein partially removing the third photoresist layer comprises ashing.