Dual-SiGe epitaxy for MOS devices

• US 7,750,338 B2
• Filed: 12/05/2006
• Issued: 07/06/2010
• Est. Priority Date: 12/05/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Yin-Pin
• Primary Examiner(s): Gurley; Lynne A
• Assistant Examiner(s): Li; Meiya
• Application Number:
  US11/633,855
• Publication Number:
  US 20080128746A1
• Time in Patent Office: 1,309 Days
• Field of Search: 257/288, 257/327, 257/344, 257/E29.05, 257/E29.012, 257/E21.43, 257/E21.431, 257/E21.438, 257/E29.085, 257/E29.266, 257 18- 20, 257/55, 257/63, 257/65, 438/37, 438/41, 438/44, 438/256, 438/300
• US Class Current: 257/19
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a gate stack on the semiconductor substrate; and

an epitaxial stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the epitaxial stressor comprises;

a first stressor region formed in a deep recess spaced apart from the gate stack; and

a second stressor region on the first stressor region formed in a shallow recess that extends under a gate spacer, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region, the first stressor region having different stress characteristics than the second stressor region.

2. The semiconductor structure of claim 1, wherein the epitaxial stressor comprises SiGe.

3. The semiconductor structure of claim 2, wherein the first stressor region has a first atomic percentage of germanium to germanium and silicon, the second stressor region has a second atomic percentage of germanium to germanium and silicon, and the second atomic percentage is higher than the first atomic percentage.

4. The semiconductor structure of claim 1, wherein the first stressor region has a first impurity concentration and the second stressor region has a second impurity concentration, and wherein the first impurity concentration is greater than the second impurity concentration.

5. The semiconductor structure of claim 1, wherein the epitaxial stressor comprises SiC.

6. The semiconductor structure of claim 1, wherein the second stressor region is closer to the channel region than the first stressor region by greater than about 5 nm.

7. The semiconductor structure of claim 1, wherein the first stressor region has a first thickness and the second stressor region has a second thickness, and wherein the second thickness is between about 20 and about 70 percent of the first thickness.

8. A semiconductor structure comprising:

a semiconductor substrate;

a gate stack on the semiconductor substrate;

a gate spacer on a sidewall of the gate stack;

a shallow epitaxial stressor disposed in a shallow recess having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the containing the shallow epitaxial stressor extends under the gate spacer; and

a deep epitaxial stressor underlying and adjoining the shallow epitaxial stressor and disposed in a deep recess in the semiconductor substrate and spaced apart from the gate stack, wherein the region of the semiconductor substrate directly underlying the gate spacer is free from the deep epitaxial stressor, the shallow epitaxial stressor being a different material than the deep epitaxial stressor.

9. The semiconductor structure of claim 8, wherein the shallow epitaxial stressor comprises SiGe, and wherein the deep epitaxial stressor comprises SiGe.

10. The semiconductor structure of claim 8, wherein the deep epitaxial stressor has a first impurity concentration, and the shallow epitaxial stressor has a second impurity concentration, and wherein the first impurity concentration is greater than the second impurity concentration.

11. The semiconductor structure of claim 8, wherein the shallow epitaxial stressor extends toward a channel region underlying the gate stack further than the deep epitaxial stressor by a distance of greater than about 5 nm.

18. The semiconductor structure of claim 9, wherein the deep epitaxial stressor has a first atomic percentage of germanium to germanium and silicon, and the shallow epitaxial stressor has a second atomic percentage of germanium to germanium and silicon, and wherein the first atomic percentage is less than the second atomic percentage.

19. The semiconductor structure of claim 8, wherein the shallow epitaxial stressor comprises SiC, and wherein the deep epitaxial stressor comprises SiC.

20. The semiconductor structure of claim 8, wherein the deep epitaxial stressor has a first thickness and the shallow epitaxial stressor has a second thickness, and wherein the second thickness is between about 20 and about 70 percent of the first thickness.

12. A semiconductor structure comprising:

a semiconductor substrate;

a gate stack on the semiconductor substrate; and

a SiGe stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the SiGe stressor comprises;

a first SiGe region formed as a first epitaxial layer in a deep recess spaced apart from the gate stack and having a first atomic percentage of germanium to germanium and silicon; and

a second SiGe region formed as a second epitaxial layer in a shallow recess that extends under the gate stack and formed on the first SiGe region and having a second atomic percentage of germanium to germanium and silicon, wherein the second atomic percentage is greater than the first atomic percentage, and wherein the second SiGe region is laterally closer to a channel region than the first SiGe region.

13. The semiconductor structure of claim 12, wherein the second atomic percentage is between about 25 percent and about 40 percent, and wherein the first atomic percentage is between about 15 percent and about 25 percent.

14. The semiconductor structure of claim 12, wherein the first atomic percentage is less than about the second atomic percentage by greater than about 5 atomic percent.

15. The semiconductor structure of claim 12, wherein the first SiGe region has a first p-type impurity concentration and the second SiGe stressor has a second p-type impurity concentration less than the first p-type impurity concentration.

16. The semiconductor structure of claim 15, wherein the first p-type impurity concentration is between about 5×

10²⁰/cm³ and about 1×

10²¹/cm³, and the second p-type impurity concentration is between about 1×

10¹⁹/cm³ and about 5×

10²⁰/cm³.

17. The semiconductor structure of claim 15, wherein second p-type impurity concentration is less than about 10 percent of the first p-type impurity concentration.