Inductively coupled integrated circuit and methods for use therewith

• US 7,750,435 B2
• Filed: 02/27/2008
• Issued: 07/06/2010
• Est. Priority Date: 02/27/2008
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza)
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): NGUYEN, DUY T V
• Application Number:
  US12/038,260
• Publication Number:
  US 20090212390A1
• Time in Patent Office: 860 Days
• Field of Search: 257/531, 257/782, 257/E27.009, 257/E23.01, 438/3, 438/455, 336/258
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A circuit includes a first integrated circuit or die having a first circuit and a first inductive interface. A second integrated circuit or die has a second circuit and a second inductive interface. The first inductive interface and the second inductive interface are aligned to magnetically communicate signals between the first circuit and the second circuit.

Claims

1. A circuit comprising:

a first integrated circuit having a first circuit and a first inductive interface; and

a second integrated circuit, coupled to the first integrated circuit, the second integrated circuit having a second circuit and a second inductive interface, wherein the first inductive interface and the second inductive interface are aligned to magnetically communicate signals between the first integrated circuit and the second integrated circuit;

wherein the first integrated circuit is bonded to the second integrated circuit via a ferromagnetic glue; and

wherein at least a portion of the ferromagnetic glue provides a magnetic communication path between the first inductive interface and the second inductive interface.

2. The circuit of claim 1 wherein the first inductive interface includes a first coil and the second inductive interface includes a second coil.

3. The circuit of claim 2 wherein the first integrated circuit includes a first substrate and wherein the first coil is at least partially implemented in a metal layer of the first substrate.

4. The circuit of claim 2 wherein the first integrated circuit includes a first die and wherein the first coil is at least partially implemented in a metal layer of the first die.

5. The circuit of claim 1 wherein the first inductive interface and the second inductive interface are aligned to magnetically communicate signals bidirectionally between the first circuit and the second circuit.

6. The circuit of claim 1 wherein the first integrated circuit and the second integrated circuit are stacked.

7. An integrated circuit comprising:

a first integrated circuit die having a first circuit and a first inductive interface; and

a second integrated circuit die, bonded to the first integrated circuit die via a ferromagnetic glue, the second integrated circuit die having a second circuit and a second inductive interface, wherein the first inductive interface and the second inductive interface are aligned to magnetically communicate signals between the first integrated circuit die and the second integrated circuit die via a communication path that includes at least a portion of the ferromagnetic glue.

8. The circuit of claim 7 wherein the first integrated circuit die is bonded to the second integrated circuit die.

9. The circuit of claim 7 wherein the first inductive interface includes a first coil and the second inductive interface includes a second coil.

10. The circuit of claim 9 wherein the first coil is at least partially implemented in a metal layer of the first integrated circuit die.

11. The circuit of claim 7 wherein the first inductive interface and the second inductive interface are aligned to magnetically communicate signals bidirectionally between the first circuit and the second circuit.

12. The circuit of claim 7 wherein the first integrated circuit die and the second integrated circuit die are stacked.

13. A method comprising:

aligning a first inductive interface of a first integrated circuit and a second inductive interface of a second integrated circuit;

bonding the first integrated circuit to the second integrated circuit using a ferromagnetic glue; and

magnetically communicating signals between a first circuit of the first integrated circuit and a second circuit of the second integrated circuit via the first inductive interface and the second inductive interface via a magnetic communication path that includes at least a portion of the ferromagnetic glue.

14. The method of claim 13 magnetically communicating signals includes bidirectionally communicating signals between the first circuit and the second circuit.

15. The method of claim 13 wherein aligning the first inductive interface of the first integrated circuit and the second inductive interface of the second integrated circuit includes stacking the first integrated circuit and the second integrated circuit.

16. The method of claim 13 wherein aligning the first inductive interface of the first integrated circuit and the second inductive interface of the second integrated circuit includes aligning a first coil of the first inductive interface with a second coil of the second inductive interface.