Same size die stacked package having through-hole vias formed in organic material

• US 7,750,452 B2
• Filed: 06/26/2007
• Issued: 07/06/2010
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Do, Byung Tai, Kuan, Heap Hoe, Chow, Seng Guan
• Primary Examiner(s): Cao; Phat X
• Assistant Examiner(s): VIEIRA, DIANA C
• Application Number:
  US11/768,869
• Publication Number:
  US 20080272470A1
• Time in Patent Office: 1,106 Days
• Field of Search: 257/777, 257/787, 257/702, 257/E23.007, 257/E23.003, 257/704, 257/701, 257/E23.178, 257/698, 257/784, 257/773, 257/689, 257/686, 257/730, 257/E23.01, 257/E23.119, 257/E23.011, 257/723, 257/676
• US Class Current: 257/686
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies.

Claims

1. A semiconductor package, comprising:

a substrate or leadframe structure;

a plurality of stacked same-size interconnected dies disposed over the substrate or leadframe structure, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material;

a plurality of bond pads formed on the top surface of each of the stacked same-size interconnected dies;

a plurality of conductive traces formed on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs; and

an encapsulant formed over a portion of the substrate or leadframe structure and the plurality of stacked same-size interconnected dies.

2. The semiconductor package of claim 1, wherein the first die of the plurality of stacked same-size interconnected dies is wire-bonded to the substrate or leadframe structure.

3. The semiconductor package of claim 2, further including a wire coupled between the substrate or leadframe structure and a terminal land.

4. The semiconductor package of claim 1, further including a conductive lid disposed over a surface of the substrate or leadframe structure.

5. The semiconductor package of claim 4, wherein the first die of the plurality of stacked same-size interconnected dies is attached to the conductive lid using a die attach adhesive material.

6. The semiconductor package of claim 1, wherein the substrate or leadframe structure is bumped to facilitate electrical connectivity.

7. The semiconductor package of claim 1 wherein the plurality of conductive THVs surround the periphery of each die.

8. A semiconductor package, comprising:

a substrate or leadframe structure having an integrated cavity;

a plurality of stacked same-size interconnected dies disposed within the integrated cavity, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material;

a plurality of bond pads formed on the top surface of each of the stacked same-size interconnected dies;

a plurality of conductive traces formed on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs;

a bond wire coupled between the second die of the stacked same-size interconnected dies and substrate or leadframe structure; and

an encapsulant formed over a portion of the substrate or leadframe structure and the stacked same-size interconnected dies.

9. The semiconductor package of claim 8, further including a conductive lid disposed over a surface of the substrate or leadframe structure.

10. The semiconductor package of claim 9, wherein the first die of the plurality of stacked same-size interconnected dies is attached to the conductive lid using a die attach adhesive material.

11. The semiconductor package of claim 8, wherein the substrate or leadframe structure is bumped to facilitate electrical connectivity.

12. The semiconductor package of claim 8 wherein the plurality of conductive THVs surround the periphery of each die.

13. A method of manufacturing a semiconductor package, comprising:

providing a substrate or leadframe structure;

providing a plurality of stacked same-size interconnected dies disposed over the substrate or leadframe structure, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material;

forming a plurality of bond pads on the top surface of each of the stacked same-size interconnected dies;

forming a plurality of conductive traces on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs; and

depositing an encapsulant formed over a portion of the substrate or leadframe structure and the plurality of dies.

14. The method of manufacture of claim 13, wherein the first die of the plurality of stacked same-size interconnected dies is wire-bonded to the substrate or leadframe structure.

15. The method of manufacture of claim 14, further including forming a wire between the substrate or leadframe structure and a terminal land.

16. The method of manufacture of claim 13, further including disposing a conductive lid over a surface of the substrate or leadframe structure.

17. The method of manufacture of claim 16, further including attaching the first die of the plurality of stacked same-size interconnected dies to the conductive lid using a die attach adhesive material.

18. The method of manufacture of claim 13, wherein the substrate or leadframe structure is bumped to facilitate electrical connectivity.

19. The method of manufacture of claim 13, wherein each of the plurality of stacked same-size interconnected dies has a substantially similar dimensional footprint.

20. The method of claim 13 wherein the plurality of conductive THVs surround the periphery of each die.

21. A method of manufacturing a semiconductor package, comprising:

providing a substrate or leadframe structure having an integrated cavity;

providing a plurality of stacked same-size interconnected dies disposed within the integrated cavity, each die having a top surface, side surface, and bottom surface, the top surface of a first die of the stacked same-size interconnected dies directly contacting the bottom surface of a second die of the stacked same-size interconnect dies, the side surface of each die being surrounded by an organic material having a plurality of conductive through-hole vias (THVs) formed in the organic material extending from a top surface of the organic material to a bottom surface of the organic material, the conductive THVs being exposed from a side surface of the organic material;

forming a plurality of bond pads on the top surface of each of the stacked same-size interconnected dies;

forming a plurality of conductive traces on the top surface of each of the stacked same-size interconnected dies between the bond pads and the conductive THVs;

forming a bond wire between the second die of the stacked same-size interconnected dies and substrate or leadframe structure; and

depositing an encapsulant formed over a portion of the substrate or leadframe structure and the plurality of dies.

22. The method of manufacture of claim 21, further including disposing a conductive lid over a surface of the substrate or leadframe structure.

23. The method of manufacture of claim 22, further including attaching the first die of the plurality of interconnected dies to the conductive lid using a die attach adhesive material.

24. The method of manufacture of claim 21, wherein the substrate or leadframe structure is bumped to facilitate electrical connectivity.

25. The method of claim 21 wherein the plurality of conductive THVs surround the periphery of each die.