Integrated circuit package system including zero fillet resin

• US 7,750,482 B2
• Filed: 02/09/2006
• Issued: 07/06/2010
• Est. Priority Date: 02/09/2006
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Pendse, Rajendra D.
• Primary Examiner(s): Chu; Chris C
• Application Number:
  US11/307,482
• Publication Number:
  US 20070182018A1
• Time in Patent Office: 1,608 Days
• Field of Search: 257/E27.137, 257/E27.144, 257/E27.161, 257/685, 257/686, 257/777, 257/787, 257/723, 438/108, 438/109, 361/760
• US Class Current: 257/778
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An integrated circuit packaging system comprised by providing a substrate with a first surface including conductive regions for receiving a flip chip die and a second surface including electrical contacts for external electrical connections. Providing the flip chip die over the substrate. Depositing a controlled volume of resin between the first surface of the substrate and the flip chip die and adhering the flip chip die to the first surface of the substrate to form the controlled volume of resin into a zero fillet resin.

Claims

1. A method of manufacturing an integrated circuit package comprising:

providing a substrate with a first surface including conductive regions for receiving a flip chip die and a second surface including electrical contacts for external electrical connections;

providing the flip chip die over the substrate;

depositing a controlled volume of resin between the first surface of the substrate and the flip chip die including applying the resin in a volume insufficient to fill the volume of space between the first surface of the substrate and the flip chip die; and

adhering the flip chip die to the first surface of the substrate to form the controlled volume of resin into a zero fillet resin contacting an interconnect between the flip chip die and the substrate.

2. The method of claim 1 wherein:

providing the flip chip die includes a die selected from digital signal processor die, application specific integrated circuit die, or micro-processor die.

3. The method of claim 1 wherein:

depositing the controlled volume of resin includes depositing a volume of resin sufficient for assuring adhesion and preventing fillet formation.

4. The method of claim 1 further comprising:

providing a wire bond die over the flip chip die.

5. The method of claim 1 wherein:

manufacturing the integrated circuit package includes forming package-on-package systems or package-in-package systems.

6. A method of manufacturing an integrated circuit package comprising:

providing a substrate with a bond finger on a first surface and solder ball connections on a second surface;

providing a flip chip die;

depositing a controlled volume of resin between the first surface of the substrate and the flip chip die including applying the resin in a volume insufficient to fill the volume of space between the first surface of the substrate and the flip chip die;

adhering the flip chip die to the first surface of the substrate to form the controlled volume of resin into a zero fillet resin;

routing a zero fillet wire bond connection to connect to the medial bond finger region closest to the flip chip die; and

depositing a molding compound.

7. The method of claim 6 wherein:

providing the substrate includes a substrate selected from printed circuit boards, package substrates, silicon substrates or integrated circuit die.

8. The method of claim 6 wherein:

forming the zero fillet resin includes a perimeter region void of resin or filled by a molding compound between the substrate and the flip chip die of about 3 mm in width.

9. The method of claim 6 wherein:

depositing a controlled volume of resin includes pre-applying the resin to the flip chip die or to the substrate.

10. The method of claim 6 wherein:

manufacturing the integrated circuit package includes forming package-on-package systems or package-in-package systems.

11. An integrated circuit packaging system comprising:

a flip chip die;

a substrate with a first surface including conductive regions for receiving the flip chip die and a second surface including electrical contacts for external electrical connections; and

a controlled volume of resin between the first surface of the substrate and the flip chip die, wherein the controlled volume of resin does not extend to the perimeter of the flip chip die, produces a zero fillet resin contacting an interconnect between the flip chip die and the substrate.

12. The system as claimed in claim 11 wherein:

the flip chip die includes a die selected from digital signal processor die, application specific integrated circuit die, or micro-processor die.

13. The system as claimed in claim 11 wherein:

the controlled volume of resin includes a volume of resin sufficient for assuring adhesion and preventing fillet formation.

14. The system as claimed in claim 11 further comprising:

a wire bond die over the flip chip die.

15. The system as claimed in claim 11 wherein:

the integrated circuit packaging system includes package-on-package systems or package-in-package systems.

16. The system as claimed in claim 11 wherein:

the substrate includes a bond finger on the first surface and solder ball connections on the second surface;

a zero fillet wire bond connection connected to a medial bond finger region closest to the flip chip die; and

a molding compound that encapsulates the packaging system.

17. The system as claimed in claim 16 wherein:

the substrate includes the substrate selected from printed circuit boards, package substrates, silicon substrates or integrated circuit die.

18. The system as claimed in claim 16 wherein:

the zero fillet resin includes a perimeter region void of resin or filled with a molding compound between the substrate and the flip chip die in the range of 1 to 3 mm in width.

19. The system as claimed in claim 16 wherein:

the controlled volume of resin is applied primarily to the flip chip die or to the substrate.

20. The system as claimed in claim 16 wherein:

the integrated circuit package includes package-on-package systems or package-in-package systems.