Pixel structure

• US 7,750,958 B1
• Filed: 03/01/2006
• Issued: 07/06/2010
• Est. Priority Date: 03/28/2005
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dierickx, Bart
• Primary Examiner(s): Tran; Nhan T
• Assistant Examiner(s): DIEP, TRUNG T
• Application Number:
  US11/366,926
• Time in Patent Office: 1,588 Days
• Field of Search: 348/213, 348/7, 348/250, 348/281, 348/294, 348/301, 348/302, 348/308, 257290-292
• US Class Current: 348/294
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

A method is disclosed for applying a first voltage to a back plate of a memory capacitor of a pixel to discharge the memory capacitor, pre-charging the memory capacitor in the pixel by applying the first voltage to a source of a pre-charge transistor while applying the first voltage to the back plate of the memory capacitor, and applying a second voltage to the back plate of the memory capacitor and the source of the pre-charge transistor, wherein the second voltage is at a higher potential than the first voltage to generate a negative gate-to-source voltage in the pre-charge transistor.

Claims

1. A method comprising:

applying a first voltage to a back plate of a memory capacitor of a pixel to discharge the memory capacitor;

pre-charging the memory capacitor in the pixel by applying the first voltage to a source of a pre-charge transistor while applying the first voltage to the back plate of the memory capacitor; and

applying a second voltage to the back plate of the memory capacitor and the source of the pre-charge transistor,

wherein the second voltage is at a higher potential than the first voltage to generate a negative gate-to-source voltage in the pre-charge transistor.

2. The method of claim 1, wherein the first voltage comprises a low supply voltage.

3. The method of claim 1, wherein the second voltage comprises a variable voltage.

4. A pixel, comprising:

a memory capacitor having a back plate; and

a pre-charge transistor coupled to the memory capacitor, the pre-charge transistor having a source,

wherein a first voltage is applied to the back plate of the memory capacitor to discharge the memory capacitor,

wherein the memory capacitor is pre-charged by applying the first voltage to the source of the pre-charge transistor while applying the first voltage to the back plate of the memory capacitor,

wherein a second voltage is applied to the back plate of the memory capacitor and the source of the pre-charge transistor, and

wherein the second voltage is at a higher potential than the first voltage to generate a negative gate-to-source voltage in the pre-charge transistor.

5. The apparatus of claim 4, further comprising means for generating the first voltage and the second voltage.

6. The pixel of claim 4, wherein the first voltage comprises a low supply voltage.

7. The pixel of claim 4, wherein the second voltage comprises a variable voltage.

8. The pixel of claim 4, comprising:

a light detecting stage,

wherein the light detecting stage comprises;

a photodiode; and

a reset transistor coupled to the photodiode; and

a sample and hold stage,

wherein the sample and hold stage comprises;

the memory capacitor and the pre-charge transistor; and

a sample transistor having a source coupled to the memory capacitor and the pre-charge transistor.

9. The pixel of claim 8, comprising:

a first amplifier coupled between the photodiode and the sample transistor; and

a second amplifier coupled between the capacitor and a row select transistor,

wherein the row select transistor is coupled to the memory capacitor.

10. The pixel of claim 9, wherein the first amplifier comprises a first source follower transistor, and

wherein the second amplifier comprises a second source follower transistor.

11. The pixel of claim 4, wherein the memory capacitor comprises a poly-diffusion capacitor.

12. The pixel of claim 11, wherein the back plate of the memory capacitor comprises the diffusion.

13. A synchronous shutter image sensor comprising a plurality of the pixels of claim 4.