Method of fabricating a liquid crystal display device, comprising forming a protective film so that one end of the protective film is contacted with one end of the transparent conductive pattern.

• US 7,751,011 B2
• Filed: 06/29/2005
• Issued: 07/06/2010
• Est. Priority Date: 12/24/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul, Lim, Joo Soo, Park, Byung Ho
• Primary Examiner(s): Schechter; Andrew
• Assistant Examiner(s): CHANG, CHARLES S
• Application Number:
  US11/168,314
• Publication Number:
  US 20060139504A1
• Time in Patent Office: 1,833 Days
• Field of Search: 349 42- 43, 349/122, 349/138, 349/141, 349/147, 349/187, 257/72
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes

Abstract

A method of fabricating a liquid crystal display device according to the present invention includes a first mask process of forming a first mask pattern group including a gate line, a gate electrode, a common line and a common electrode on a substrate, a second mask process of forming a gate insulating film on the first mask pattern group and a semiconductor pattern and an opaque conductive pattern on the gate insulating film, and a third mask process of forming a transparent conductive pattern on the opaque conductive pattern and forming a protective film, wherein one end of the protective film is contacted with one end of the transparent conductive pattern.

Claims

1. A method of fabricating a liquid crystal display device, comprising:

a first mask process of forming a first mask pattern group including a gate line, a gate electrode, a common line and a common electrode on a substrate;

a second mask process of forming a gate insulating film on the first mask pattern group and a semiconductor pattern and an opaque conductive pattern on the gate insulating film; and

a third mask process of forming a transparent conductive pattern on the opaque conductive pattern so that a data line crossing the gate line, a source electrode and a drain electrode are formed of a double-layer structure having the opaque conductive pattern and the transparent conductive pattern, and a pixel electrode is extended from the transparent conductive pattern of the drain electrode to form a horizontal electric field with the common electrode, and forming a protective film so that one end of the protective film is contacted with one end of the transparent conductive pattern.

2. The method as claimed in claim 1, wherein:

the first mask process further includes forming a lower pad electrode to be connected to at least one of the gate line, the data line and the common line, wherein each of the gate line, the data line and the common line has a multiple-layer structure in which at least two conductive layers are overlapped

the second mask process further includes forming a contact hole passing through the gate insulating film to expose the lower pad electrode, and

the third mask process further includes forming an upper pad electrode to be connected to the lower pad electrode via the contact hole, from the upper pad electrode being formed of the transparent conductive pattern.

3. The method as claimed in claim 1, wherein:

the first mask process includes forming a data link extended from the lower pad electrode to be connected to the data line,

the second mask process includes forming a second contact hole to expose the data link, and

the third mask process includes forming a contact electrode extended from the transparent conductive pattern of the data line to be connected to the data link via the second contact hole.

4. The method as claimed in claim 3, wherein the contact electrode is integral to the upper pad electrode.

5. The method as claimed in claim 3, wherein the upper pad electrode and the contact electrode borders with the protective film.

6. The method as claimed in claim 3, wherein the gate line, the gate electrode, the common line, the common electrode, the lower pad electrode and the data link include one of a single-layer structure formed of one of Mo, Ti, Cu, AlNd, Al, Cr, a Mo alloy, a Cu alloy and an Al alloy, and a multiple-layer structure having at least two layers thereof.

7. The method as claimed in claim 1, wherein the transparent conductive pattern encloses the opaque conductive pattern.

8. The method as claimed in claim 3, wherein the second mask process includes:

substantially sequentially forming a gate insulating film covering the first mask pattern group, an amorphous silicon layer, an amorphous silicon layer doped with an impurity and an opaque conductive layer;

forming photo-resist patterns having a different thickness by a photolithography using at least one of a half tone mask and a diffractive exposure mask; and

forming first and second contact holes passing through the opaque conductive layer and the gate insulating film, the opaque conductive pattern, and the semiconductor pattern having an active layer and an ohmic contact layer by an etching process using the photo-resist pattern.

9. The method as claimed in claim 1, wherein the third mask process includes:

forming a transparent conductive layer on the gate insulating film;

forming a photo-resist pattern by the photolithography;

forming the transparent conductive pattern by an etching process using the photo-resist pattern as a mask;

removing the opaque conductive pattern and an ohmic contact layer exposed through the transparent conductive pattern;

substantially entirely forming a protective film covering the photo-resist pattern; and

removing the photo-resist pattern with the protective film.

10. The method as claimed in claim 9, wherein the protective film is formed using a sputtering.

11. The method as claimed in claim 9, wherein the transparent conductive pattern is over-etched than the photo-resist pattern.

12. The method as claimed in claim 1, further comprising:

forming a storage capacitor such that the pixel electrode overlaps with a portion of the common electrode having the gate insulating film there between.