Semiconductor device and method for selection and de-selection of memory devices interconnected in series
First Claim
1. A memory device for use in an arrangement of memory devices interconnected in series, the memory device comprising:
- a first input for receiving a command input signal containing a command having an identification number;
a second input for receiving a first strobe signal indicating the start of the command;
a third input for receiving clock input;
a fourth input for receiving a second strobe signal, andlogic circuitry configured to;
de-select the memory device in response to the first strobe signal to place the memory device in a de-selected state;
determine whether the identification number of the command matches a device address associated with the memory device;
in response to a determination result, place the memory device in a selected state,forward the command input signal and the first strobe signal with a delay related to clock cycle latency while the memory device is in the de-selected state;
refrain from for warding the command input signal and the first strobe signal while the memory device is in the selected state; and
forward the second strobe signal with a delay related to a latency that is substantially equal to the latency of a delayed version of the first strobe signal, the second strobe signal containing data enabling data output from the memory device in the selected state.
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Accused Products
Abstract
A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared to the memory device'"'"'s device address. Delayed versions of the command strobe signal and the command are forwarded while the memory device is in the de-selected state. If the ID number matches the device address with reference to the ID number, the memory device is placed in a selected state. In the selected state, the memory device may refrain from forwarding the delayed versions of the command strobe signal and the command, such that if there is a match, a truncated part of the command is forwarded before the memory device is placed in the selected state.
92 Citations
20 Claims
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1. A memory device for use in an arrangement of memory devices interconnected in series, the memory device comprising:
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a first input for receiving a command input signal containing a command having an identification number; a second input for receiving a first strobe signal indicating the start of the command; a third input for receiving clock input; a fourth input for receiving a second strobe signal, and logic circuitry configured to; de-select the memory device in response to the first strobe signal to place the memory device in a de-selected state; determine whether the identification number of the command matches a device address associated with the memory device; in response to a determination result, place the memory device in a selected state, forward the command input signal and the first strobe signal with a delay related to clock cycle latency while the memory device is in the de-selected state; refrain from for warding the command input signal and the first strobe signal while the memory device is in the selected state; and forward the second strobe signal with a delay related to a latency that is substantially equal to the latency of a delayed version of the first strobe signal, the second strobe signal containing data enabling data output from the memory device in the selected state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method in a memory device in an arrangement of memory devices interconnected in series, the method comprising:
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receiving a command input signal containing a command having an identification number; receiving a first strobe signal indicating the start of the command; de-selecting the memory device when the first strobe signal is received to place the memory device in a de-selected state; determining whether the identification number of the command matches a device address associated with the memory device; placing the memory device in a selected state if the identification number of the command matches the device address associated with the memory device, forwarding a delayed version of the first strobe signal with a delay relating to a clock cycle latency while the memory device is in the de-selected state; receiving a second strobe signal containing data strobes enabling data output from the memory device in the selected state; and forwarding a delayed version of the second strobe signal with a latency that is substantially equal to the latency of the delayed version of the first strobe signal. - View Dependent Claims (17, 18, 19, 20)
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Specification