Video encoding and video/audio/data multiplexing device
First Claim
1. A single chip digital signal processing device for real time video/audio compression, said device comprising:
- a motion estimation processor which receives video data and produces a motion analysis therefrom;
a digital signal processor which, according to said motion analysis, compresses video data that has been processed by the video input processor; and
a bitstream processor which formats video data that has been compressed by the digital signal processor to produce a video bitstream;
wherein said motion estimation processor operates on macroblock a of frame I, said digital signal processor operates on macroblock b of frame I, and said bitstream processor operates on macroblock c of frame I concurrently, wherein a≧
b≧
c.
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Accused Products
Abstract
The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.
37 Citations
7 Claims
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1. A single chip digital signal processing device for real time video/audio compression, said device comprising:
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a motion estimation processor which receives video data and produces a motion analysis therefrom; a digital signal processor which, according to said motion analysis, compresses video data that has been processed by the video input processor; and a bitstream processor which formats video data that has been compressed by the digital signal processor to produce a video bitstream; wherein said motion estimation processor operates on macroblock a of frame I, said digital signal processor operates on macroblock b of frame I, and said bitstream processor operates on macroblock c of frame I concurrently, wherein a≧
b≧
c. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification