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Fractional voltage converter

  • US 7,751,879 B2
  • Filed: 01/05/2007
  • Issued: 07/06/2010
  • Est. Priority Date: 04/12/2004
  • Status: Active Grant
First Claim
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1. An implantable pulse generator for generating electrical pulses for stimulating tissue of a patient, comprising:

  • pulse generating circuitry for generating pulses and delivering the pulses to outputs of the implantable pulse generator;

    a controller for controlling the pulse generating circuitry;

    wherein the pulse generating circuitry comprises a voltage multiplier for multiplying a battery voltage, the voltage multiplier including multiple outputs, wherein a first output of the multiple outputs provides a voltage that is programmably selectable from a plurality of voltages including non-integer multiples of the battery voltage, wherein a second output of the multiple outputs provides a voltage that is a fixed multiple of the battery voltage;

    wherein the controller controls the pulse generator circuitry to generate a first pulse for stimulation of the patient using a first output of the multiple outputs and controls the pulse generator circuitry to generate a second pulse to discharge output capacitors of residual charge from the first pulse using a second output of the multiple outputs;

    wherein the voltage multiplier comprises;

    a plurality of capacitors; and

    switching circuitry for selectively connecting to the plurality of capacitors, wherein said switching circuitry comprises a plurality of controllable switches, wherein the plurality of controllable switches includes at least a first switch having a higher relative voltage characteristic and a second switch having a lower relative voltage characteristic;

    clock conversion circuitry for converting a received clock into respective level-shifted clocks for application to the plurality of controllable switches, wherein the clock conversion circuitry up-shifts the received clock to a maximum level for generation of a level-shifted clock for application to the first switch and, then, down-shifts from the maximum level for generation of a level-shifted clock for application to the second switch.

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