Random number generator and generation method

• US 7,752,247 B2
• Filed: 08/21/2006
• Issued: 07/06/2010
• Est. Priority Date: 02/14/1995
• Status: Expired due to Fees

• Current Assignee: The Quantum World Corporation (Altitude Capital Partners)
• Original Assignee: The Quantum World Corporation (Altitude Capital Partners)
• Inventors: Wilber, Scott A.
• Primary Examiner(s): Mai; Tan V
• Application Number:
  US11/507,959
• Publication Number:
  US 20070033242A1
• Time in Patent Office: 1,415 Days
• Field of Search: 708/255
• US Class Current: 708/255
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes

Abstract

An RNG circuit is connected to the parallel port of a computer. The circuit includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range. A low-frequency cut-off is selected to maintain high band-width yet eliminate the 1/f amplifier noise tail. A CMOS comparator with a 10 nanosecond rise time converts the analog signal to a binary one. A shift register converts the serial signal to a 4-bit parallel one at a sample rate selected at the knee of the serial dependence curve. Two levels of XOR defect correction produce a BRS at 20 kHZ, which is converted to a 4-bit parallel word, latched and buffered. The entire circuit is powered from the data pins of the parallel port. A device driver interface in the computer operates the RNG. The randomness defects with various levels of correction and sample rates are calculated and the RNG is optimized before manufacture.

Claims

1. A general purpose computer that generates true random numbers and utilizes at least some of the true random numbers in an application program, said computer comprising:

a true random number generator circuit, mounted on a motherboard of said general purpose computer and receiving power from said motherboard, said true random number generator circuit including an entropy source that, in conjunction with a clock signal, generates random numbers, wherein said entropy source is selected from the group consisting of a thermal noise source and a semiconductor noise source;

a memory buffer that stores said random numbers;

an interface that interfaces with said random number generator circuit, wherein said interface automatically tests said true random number generator circuit when said general purpose computer is turned on; and

an application program installed on said general purpose computer that is capable of performing an operation to read random numbers from said memory buffer, wherein said application program utilizes at least some of said read random numbers within the context of said application program.

2. A computer as in claim 1, wherein said interface includes a device driver that interfaces said application program to said true random number generator circuit.

3. A computer as in claim 1, wherein said clock signal is generated within said true random number generator circuit.

4. A computer as in claim 3, wherein said entropy source generates an analog signal that is sampled using said clock signal to generate said true random numbers.

5. A computer as in claim 3, wherein said clock signal is independent of any other clock signal generated on said motherboard.

6. A computer as in claim 1, wherein the context of said application program is a cryptography application, and wherein said random numbers are generated in real-time for consumption by said application program.

7. A computer as in claim 1, wherein said true random number generator circuit includes digital circuitry that performs a randomness correction on said random numbers.

8. A computer as in claim 1, wherein said thermal noise source comprises a resistor that generates an analog signal with an amplitude that is substantially flat relative to frequency, and wherein said true random number generator circuit includes a low-noise amplifier that amplifies said analog signal.

9. A computer as in claim 1, wherein at least a portion of said true random number generator circuit is electromagnetically shielded.

10. A true random number generator system, comprising:

a hardware true random number generator circuit that implements a noise source for generating a true random sequence of signals, wherein said noise source is selected from the group consisting of a thermal noise source and a semiconductor noise source; and

a personal computer including a true random number generator circuit interface, said interface consisting of one or more of the following;

a device driver, a portion of an operating system of said personal computer, or a program stored in a BIOS memory of said personal computer;

wherein said interface further comprises software for locating and testing said hardware true random number generator circuit when said personal computer is turned on or when said hardware true random number generator circuit is initialized.

12. A system as in claim 10, wherein said interface comprises an operating system that performs an initialization routine for said hardware true random number generator circuit when said personal computer is turned on.

13. A system as in claim 10, wherein said personal computer includes an application program that consumes numbers provided by said hardware true random number generator circuit.

14. A system as in claim 10, wherein said application program issues a request to read random numbers provided by said hardware true random number generator circuit.

15. A system as in claim 10, wherein said personal computer includes a processor that reads random numbers from a memory buffer into which said hardware true random number generator circuit writes random numbers.

16. A system as in claim 15, wherein said processor tests said read random numbers to determine if they are sufficiently random.

17. A system as in claim 15, wherein said processor reads said random numbers when needed by said application program.

18. A system as in claim 10, wherein an interrupt is produced by said hardware true random number generator circuit when random numbers have been generated, which causes said random numbers to be stored into a memory buffer.

20. A system as in claim 10, wherein said interface is separate from an application program.

21. A system as in claim 10, wherein said hardware true random number generator circuit is pre-assembled on the motherboard of said personal computer.

22. A system as in claim 21, wherein said hardware true random number generator circuit receives operating power from a power connection to said motherboard.

23. A system as in claim 22, wherein said hardware true random number generator circuit includes a dedicated clock circuit that is independent of any other clock circuit on said motherboard, and which is used to sample said noise source.

24. A system as in claim 22, wherein said true random number generator system provides random numbers having a |B2|<

=0.002, |SD(1)|<

=0.0004 and |SD(2)|<

=0.0004 with a 95% confidence level, where B2 is the bias in the 1, 0 probability of the generator, SD(1) is the serial dependence for single sample periods and SD(2) is the serial dependence for two sample periods of the generator.

11. A system as in 10, wherein said interface comprises a device driver, and said device driver tests said hardware true random number generator circuit automatically each time said personal computer is turned on.

19. A system as in 78, wherein said interface is incorporated into an application program.

25. A general purpose personal computer, said personal computer including a processor, a motherboard, operating system software, and at least one application program, said personal computer comprising:

a hardware true random number generator circuit mounted on said motherboard and receiving power from said motherboard, wherein said hardware true random number generator circuit includes a non-deterministic analog noise source and a dedicated clock circuit that generates a clock signal that is used to sample said non-deterministic analog noise source to generate random numbers;

a memory buffer into which said random numbers are stored after being provided by said hardware true random number generator circuit;

a device driver that interfaces said hardware true random number generator circuit to said application program, wherein said processor reads said random numbers from said memory buffer in response to a request from said application program to enable utilization of said random numbers by said application program.

27. A system as in claim 25 wherein said operating system initializes said hardware true random number generator circuit when the personal computer is turned on.

28. A system as in claim 25, wherein said processor reads said random numbers when needed by said application program.

29. A system as in claim 25, wherein an interrupt is produced by said hardware true random number generator circuit when random numbers have been generated, which causes said random numbers to be stored into a memory buffer.

30. A system as in claim 25, wherein said dedicated clock circuit is independent of all other clock circuitry on said motherboard.

31. A system as in claim 25, wherein at least a portion of said hardware true random number generator circuit is electromagnetically shielded.

32. A personal computer as in claim 31, wherein the shielding includes a ground plane.

26. A personal computer as in 25, wherein said device driver tests said hardware true random number generator circuit automatically when the personal computer is turned on.