Flash memory storage system and method

• US 7,752,382 B2
• Filed: 12/28/2005
• Issued: 07/06/2010
• Est. Priority Date: 09/09/2005
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Murin, Mark, Eyal, Arik, Lasser, Menahem
• Primary Examiner(s): Thai; Tuan V
• Assistant Examiner(s): CHOE, YONG J
• Application Number:
  US11/318,906
• Publication Number:
  US 20070061502A1
• Time in Patent Office: 1,651 Days
• Field of Search: 711/103, 365/185.03, 365/185.24, 365/185.29, 365/185.33
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells.

Claims

1. A method for storing data in a flash memory storage system having a controller and a memory array, the method comprising:

a. dedicating a first group of memory cells of a memory array, such that each of said first group of memory cells stores a first number of bits;

b. dedicating a second group of memory cells of the memory array, such that each of said second group of memory cells stores a second number of bits, wherein said second number of bits is greater than said first number of bits, and said first group of memory cells and said second group of memory cells are disjoint;

c. writing data to said first group of memory cells;

d. copying the data from said first group of memory cells into said second group of memory cells; and

e. applying wear leveling to said memory cells of said first group of memory cells separately from said memory cells of said second group of memory cells, so as to evenly distribute wear of said first group of memory cells within themselves independent of wear of said second group of memory cells,

wherein respective numbers of said memory cells of said first and second groups of memory cells are selected so that a ratio between said respective number of said memory cells of said second group of memory cells and said respective number of said memory cells of said first group of memory cells is equal to a ratio between an endurance of said first group of memory cells and an endurance of said second group of memory cells multiplied by a ratio between said first number of bits and said second number of bits.

2. The method of claim 1 further comprising:

f. applying wear leveling to said memory cells of said second group of memory cells separately from said memory cells of said first group of memory cells, so as to evenly distribute wear of said second group of memory cells within themselves independent of said wear of said first group of memory cells.

3. The method of claim 1, wherein said first number of bits is one and said second number of bits is two.

4. The method of claim 1, wherein said first number of bits is one and said second number of bits is four.

5. A flash memory storage system comprising:

a. a memory array containing a plurality of memory cells;

b. a controller for controlling said memory array by dedicating a first group of memory cells from among said plurality of memory cells to store a first number of bits per cell and dedicating a second group of memory cells from among said plurality of memory cells to store a second number of bits per cell, wherein said second number is greater than said first number, and said first group of memory cells and said second group of memory cells are disjoint; and

c. a mechanism for applying wear leveling to said memory cells of said first group of memory cells separately from said memory cells of said second group of memory cells, so as to evenly distribute wear of said first group of memory cells within themselves independent of wear of said second group of memory cells,

wherein said controller selects respective numbers of said memory cells of said first and second groups of memory cells to that a ratio between said respective number of said memory cells of said second group of memory cells and said respective number of said memory cells of said first group of memory cells is equal to a ratio between an endurance of said first group of memory cells and an endurance of said second group of memory cells multiplied by a ratio between said first number of bits and said second number of bits.

6. The flash memory storage system of claim 5, further comprising a mechanism for applying wear leveling to said memory cells of said second group of memory cells separately from said memory cells of said first group of memory cells, so as to evenly distribute wear of said second group of memory cells within themselves independent of said wear of said first group of memory cells.

7. The flash memory storage system of claim 5, wherein said mechanism for applying said wear leveling is included in said controller.

8. The flash memory storage system of claim 6, wherein said mechanism for applying said wear leveling is included in said controller.

9. The flash memory storage system of claim 5, wherein said controller is further operative to store data in said first group of memory cells and subsequently to copy said data into said second group of memory cells.

10. The flash memory storage system of claim 5, wherein said first number of bits is one and said second number of bits is two.

11. The flash memory storage system of claim 5, wherein said first number of bits is one and said second number of bits is four.