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Processes, circuits, devices, and systems for branch prediction and other processor improvements

  • US 7,752,426 B2
  • Filed: 08/24/2005
  • Issued: 07/06/2010
  • Est. Priority Date: 08/30/2004
  • Status: Active Grant
First Claim
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1. A processor for processing instructions comprising a pipeline including a fetch stage and an execute stage;

  • a first storing circuit associated with said fetch stage and operable to store a history of actual branches; and

    a second storing circuit associated with said fetch stage and operable to store a pattern of predicted branches, said pattern comprising a plurality of bits wherein each bit in said plurality of bits corresponds to a predicted taken or predicted not taken behavior of a respective branch, said second storing circuit coupled to said first storing circuit, said execute stage coupled back to said first storing circuit; and

    a third storing circuit readable for branch Taken and Not-Taken information indexed on read by a pattern from said second storing circuit and operable to supply a predicted taken bit, and update logic circuitry operable to supply an updated pattern to said second storing circuit including at least some bits of a pattern from said second storage circuit and the predicted taken bit from said third storing circuit.

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