Design structure and system for identification of defects on circuits or other arrayed products
First Claim
1. A method implemented by at least one computer comprising:
- at least one computer obtaining defect characteristic data;
the at least one computer obtaining chip circuit design data across a whole semiconductor chip layer, the circuit design data comprising design shapes;
a memory accessible by the at least one computer specifying a probability relationship across the whole semiconductor chip layer between the defect characteristic data and the chip circuit design data, wherein said probability relationship includes at least one risk factor of the defect characteristic data relative to the design shapes, wherein the risk factor is weighted for a specific physical location along the semiconductor layer and the risk factor relates to inoperability of an individual semiconductor chip;
the at least one computer estimating probability of inoperability of the semiconductor chip for said probability relationship based on the defect characteristic data and the chip circuit design data;
the at least one computer generating a probability model comprising an accumulated probability of inoperability of the semiconductor chip for all defects of the defect characteristic data;
the at least one computer applying the generated probability model to a batch of semiconductor chips made with the chip circuit design data using actual defects measured in the batch; and
the at least one computer outputting a predicted yield based on the applied probability model.
3 Assignments
0 Petitions
Accused Products
Abstract
A system and method is disclosed for assessing a probability of failure of operation of a semiconductor wafer. The method includes inputting risk factor data into a memory and inputting a plurality of wafers into a semiconductor fabrication manufacturing process. A subset of wafers is select to obtain a sample population and at least one region of each wafer of the sample population is inspected. Circuit design data associated with each wafer of the sample population is obtained and one or more defects that present an increased risk to the operation of a particular wafer are identified. The identification is a function of the risk factor data, the inspecting step and the circuit design data. A probability of semiconductor wafer failure is calculated.
48 Citations
25 Claims
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1. A method implemented by at least one computer comprising:
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at least one computer obtaining defect characteristic data; the at least one computer obtaining chip circuit design data across a whole semiconductor chip layer, the circuit design data comprising design shapes; a memory accessible by the at least one computer specifying a probability relationship across the whole semiconductor chip layer between the defect characteristic data and the chip circuit design data, wherein said probability relationship includes at least one risk factor of the defect characteristic data relative to the design shapes, wherein the risk factor is weighted for a specific physical location along the semiconductor layer and the risk factor relates to inoperability of an individual semiconductor chip; the at least one computer estimating probability of inoperability of the semiconductor chip for said probability relationship based on the defect characteristic data and the chip circuit design data; the at least one computer generating a probability model comprising an accumulated probability of inoperability of the semiconductor chip for all defects of the defect characteristic data; the at least one computer applying the generated probability model to a batch of semiconductor chips made with the chip circuit design data using actual defects measured in the batch; and the at least one computer outputting a predicted yield based on the applied probability model. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory embodying a computer program that is readable by a computer for performing actions directed toward assessing a probability of failure of a semiconductor chip due to at least one defect, the actions comprising:
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from inputs of defect characteristic data and chip circuit design data across a whole semiconductor chip layer, the circuit design data comprising design shapes, specifying a probability relationship across the whole semiconductor chip layer between the defect characteristic data and the chip circuit design data, wherein said probability relationship includes at least one risk factor of the defect characteristic data relative to the design shapes, wherein the risk factor is weighted for a specific physical location along the semiconductor layer and the risk factor relates to inoperability of an individual semiconductor chip; estimating probability of inoperability of the semiconductor chip for said probability relationship based on the defect characteristic data and the chip circuit design data; and generating a probability model comprising an accumulated probability of inoperability of the semiconductor chip for all defects of the defect characteristic data; applying the generated probability model to a batch of semiconductor chips made with the chip circuit design data using actual defects measured in the batch; and outputting a predicted yield based on the applied probability model. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification