Gaming chip communication system and method

• US 7,753,779 B2
• Filed: 06/30/2006
• Issued: 07/13/2010
• Est. Priority Date: 06/16/2006
• Status: Expired due to Fees

• Current Assignee: Sg Gaming, Inc. (Light & Wonder Incorporated)
• Original Assignee: Bally Gaming Incorporated (Light & Wonder Incorporated)
• Inventors: Shayesteh, Hamid
• Primary Examiner(s): Hotaling; John M
• Assistant Examiner(s): Rowland; Steve
• Application Number:
  US11/479,988
• Publication Number:
  US 20070293303A1
• Time in Patent Office: 1,474 Days
• Field of Search: 463/25, 340/572.1, 340/572.7, 235/380
• US Class Current: 463/25
• CPC Class Codes: G07F 17/32 for games, toys, sports, or amusements
• CPC Class Codes: G07F 17/3251 involving media of variable value, e.g. programmable cards, programmable tokens

Abstract

A system and method for a gaming chip communication includes a memory configured to store chip information, a first antenna communicatively coupled to the memory and configured to receive a first radio frequency (RF) signal that includes at least previous stack information, a second antenna operable to communicate a second RF signal that comprises the previous stack information and the chip information, and where the first antenna is further configured to communicate an RF acknowledgement signal to a communication system that transmitted the first RF signal in response to the second antenna communicating the second RF signal.

Claims

1. A radio frequency (RF) gaming chip communication system, comprising:

a first gaming chip;

a processor-readable memory carried by the first gaming chip gaming chip and configured to store chip information and instructions;

a first antenna carried by the first gaming chip, communicatively coupled to the processor-readable memory, that receives a first radio frequency (RF) signal that comprises at least previous stack information from a second gaming chip, wherein the at least previous stack information corresponds to at least a portion of respective chip information of the second gaming chip; and

a second antenna carried by the first gaming chip that communicates a second RF signal that comprises current stack chip information; and

a processing system having at least one processor carried by the first gaming chip and communicatively coupled to the processor-readable memory and to the first and the second antennas, wherein the instructions, when executed by the at least one processor, cause the at least one processor to;

generate current stack information based at least on a combination of at least a portion of the previous stack information and at least a portion of the chip information,

provide the second antenna with the second RF signal, and

provide the first antenna with an RF acknowledgement signal in response to receipt by the first antenna of the first RF signal, wherein the first antenna communicates an RF acknowledgement signal to the second gaming chip that transmitted the first RF signal; and

wherein the first antenna has a communication range and the second antenna have co-extensive communication ranges.

2. The RF gaming chip communication system of claim 1, further comprising:

a first transceiver carried by the first gaming chip, communicatively coupled to the processor-readable memory and the first antenna, and configured to communicate at least the received previous stack information to the processor-readable memory in response to receiving the first RF signal; and

a second transceiver carried by the first gaming chip and communicatively coupled to the processor-readable memory and the second antenna, and configured to communicate the previous stack information and the chip information to the second antenna.

3. The RF gaming chip communication system of claim 2 wherein the second transceiver comprises:

a second receiver; and

a second transmitter.

4. The RF gaming chip communication system of claim 1, further comprising:

a transceiver carried by the first gaming chip and communicatively coupled to the processor-readable memory, the first antenna, and the second antenna, and configured to communicate at least the previous stack information received from the first antenna to the processor-readable memory in response to receiving the first RF signal, and configured to communicate the previous stack information and the chip information to the second antenna.

5. The RF gaming chip communication system of claim 1 wherein the first antenna comprises:

a first directional antenna communicatively coupled to the processor-readable memory and configured to receive a first radio frequency (RF) signal that comprises at least previous stack information when aligned in a direction substantially perpendicular to a face of the first gaming chip, and

wherein the second antenna comprises;

a second directional antenna configured to communicate a second RF signal that comprises the previous stack information and the chip information in a direction substantially perpendicular to an opposing face of the first gaming chip.

6. The RF gaming chip communication system of claim 1, further comprising:

a gaming chip body that has the processing system enclosed therein; and

wherein the processing system is configured to receive the previous stack information and the instructions, when executed by the at least one processor, cause the at least one processor to associate at least chip information for the gaming chip body to with the previous stack information.

7. The RF gaming chip communication system of claim 6, wherein the instructions, when executed by the at least one processor, cause the at least one processor to add a chip value of the gaming chip body to a value of chips in the previous stack information to determine a current stack value.

8. The RF gaming chip communication system of claim 1, further comprising:

a third antenna carried by the first gaming chip and communicatively configured to receive an electromagnetic power signal from a remote power antenna and transmitter; and

a power source carried by the first gaming chip and electrically coupled to at least the processing system and the third antenna, configured to convert the received electromagnetic signal into electrical power, and configured to supply the electrical power used by at least one component of the first gaming chip.

9. The RF gaming chip communication system of claim 1, further comprising:

a chip value residing in the processor-readable memory and associated with a value of the gaming chip body,

wherein the previous stack information comprises a previous stack value, wherein the instructions, when executed by the at least one processor, cause the at least one processor to add the previous stack value to the chip value to determine a current stack value, and wherein in the second RF signal comprises the current stack value.

10. The RF gaming chip communication system of claim 9 wherein the second gaming chip includes a respective processor-readable memory carried by the second gaming chip that stores a respective chip value associated with a value of the second gaming chip, and wherein the second gaming chip is configured to if determine a respective current stack value equals the respective chip value associated with the second gaming chip and to include the respective current stack value in the previous stack information that is communicated to the first gaming chip via the first radio frequency (RF) signal.

11. The RF gaming chip communication system of claim 9 wherein the previous stack value corresponds to a total monetary value of a plurality of preceding gaming chips, and wherein the chip value corresponds to a monetary value of the gaming chip body.

12. The RF gaming chip communication system of claim 9 wherein the previous stack value corresponds to a previous index value for a plurality of preceding gaming chips, wherein the chip value corresponds to a chip index value of the gaming chip body, wherein the previous index value is incremented by the chip index value to determine a current index value, and wherein in the second RF signal comprises the current index value.

13. The RF gaming chip communication system of claim 1, further comprising:

an identifier that uniquely identifies the gaming chip body residing in the processor-readable memory,

wherein the second RF signal further comprises the identifier.

14. The RF gaming chip communication system of claim 13 wherein identifier further comprises:

metadata corresponding to information of interest.

15. The RF gaming chip communication system of claim 1, further comprising:

a first stack pointer value stored in the processor-readable memory,

wherein the second RF signal further comprises an increment value, and wherein a pointer in the processor-readable memory is incremented by the increment value to a second stack pointer value, and wherein the second RF interrogation signal further comprises the second stack pointer value.

16. The RF gaming chip communication system of claim 15 wherein the first stack pointer value corresponds to a chip value associated with the gaming chip body, wherein the increment value corresponds to a total value of a plurality of preceding gaming chips, and wherein the second stack pointer value corresponds to a current value of the plurality of stack of gaming chips.

17. The RF gaming chip communication system of claim 1 wherein the RF acknowledgement signal indicates to the second gaming chip that the first gaming chip has received the first RF signal.

18. The RF gaming chip communication system of claim 1 wherein the second antenna is further configured to receive a second RF acknowledgement signal from an adjacent second gaming chip that indicates that the adjacent second gaming chip has received the second RF signal.

19. The RF gaming chip communication system of claim 18 where, upon failure of the second antenna to receive the second RF acknowledgement signal from the adjacent second gaming chip within a time period, at least the first antenna is further configured to communicate a third RF signal corresponding to a current total value to at least one gaming table receiver.

20. The RF gaming chip communication system of claim 18 wherein, upon a failure of the second antenna to receive the second RF acknowledgement signal from the adjacent second gaming chip within a defined time period, at least the second antenna is further configured to communicate a third RF signal corresponding to the current total value to at least one gaming table receiver.

57. The RF gaming chip communication system of claim 1, further comprising:

a transceiver carried by the gaming chip and communicatively coupled to the processor-readable memory, the first antenna and the second antenna, and configured to communicate at least the received previous stack information to the processor-readable memory in response to receiving the first RF signal and to communicate the previous stack information and the chip information to the second antenna.

21. A method for communicating information with at least a first and a second gaming chips, the method comprising:

receiving a first radio frequency (RF) signal that comprises previous stack information with a first antenna positioned at least proximate to a first side of a first gaming chip and carried by the first gaming chip, wherein the first radio frequency (RF) signal is received from a second gaming chip, and wherein the previous stack information includes chip information of the second gaming chip;

combining chip information of the first gaming chip with the previous stack information to generate current stack information;

transmitting a second RF signal that comprises the current stack information with a second antenna positioned at least proximate to a second side of the first gaming chip and carried by the first gaming chip; and

transmitting a first RF acknowledgement signal to the second gaming chip that transmitted the first RF signal.

22. The method of claim 21 wherein transmitting the RF acknowledgement signal is performed in response to transmitting the second RF signal.

23. The method of claim 21 wherein the second antenna does not respond to the first RF signal.

24. The method of claim 21

wherein receiving a first radio frequency (RF) signal includes

receiving the first RF signal with a first transceiver which is responsive to the received first RF signal;

and wherein transmitting a second RF signal includes

transmitting the second RF signal with a second transceiver,

wherein the second antenna and the second transceiver are not responsive to the first RF signal.

25. The method of claim 21, further comprising:

adding a chip value associated with the first gaming chip to a previous stack value residing in the previous stack information to determine a current stack value,

wherein the second RF signal comprises the determined current stack value.

26. The method of claim 25 wherein the previous stack value corresponds to a total monetary value of a plurality of preceding gaming chips, and wherein the chip value corresponds to a monetary value of the first gaming chip.

27. The method of claim 21, further comprising:

receiving a second RF acknowledgement signal from an adjacent third gaming chip that acknowledges receipt of the transmitted second RF signal.

28. The method of claim 21, further comprising:

waiting a time period for reception of a second RF acknowledgement signal from an adjacent third gaming chip that acknowledges receipt of the transmitted second RF signal; and

upon expiration of the time period without receiving the second RF acknowledgement signal, transmitting a third RF signal to at least one gaming table receiver, wherein the third RF signal comprises at least the current stack information.

29. The method of claim 21, further comprising:

receiving electromagnetic energy;

converting the received electromagnetic energy into electrical power; and

providing the electrical power to at least one component of the gaming chip such that the component has sufficient power for operation.

30. A radio frequency (RF) gaming chip communication system, comprising:

a plurality of gaming chips arranged in a first stack of gaming chips with a first side of each gaming chip adjacent to a second side of another gaming chip, each respective gaming chip of the plurality of gaming chips comprising;

a processor-readable memory carried by the respective gaming chip and configured to store chip information and instructions for communicating stack information to and from at least other respective gaming chips of the plurality of gaming chips;

a first antenna and a first transceiver communicatively coupled together and positioned in proximity to the first side of the respective gaming chip carried by the respective gaming chip and communicatively coupled to the processor-readable memory, configured to respond to a first radio frequency (RF) signal communicated by an adjacent gaming chip in the first stack, wherein the first RF signal comprises previous stack information, and wherein the first antenna and the first transceiver are further configured to communicate the previous stack information to the processor-readable memory; and

a second antenna and a second transceiver communicatively coupled together and positioned in proximity to the second side of the respective gaming chip carried by the respective gaming chip and communicatively coupled to the processor-readable memory, and configured to transmit a second RF signal comprising current stack information, wherein the current stack information corresponds to the previous stack information and the chip information of the respective gaming chip, and

at least one processor positioned between the first side and the second side of the respective gaming chip and communicatively coupled to the processor-readable memory, wherein the instructions, when executed by the at least one processor, cause the at least one processor to;

receive at least a portion of the first radio frequency (RF) signal, generate the current stack information based at least on the previous stack information and the chip information of the respective gaming chip, and provide at least the current stack information to the second antenna; and

an interrogator antenna and an interrogator transceiver configured to initially communicate an interrogation RF signal to the plurality of gaming chips that are arranged in the first stack, wherein one respective gaming chip in the first stack that is closest to the interrogator antenna and the interrogator transceiver is responsive to the interrogation RF signal, and wherein other gaming chips of the first stack are not responsive to the interrogation RF signal.

31. The RF gaming chip communication system of claim 30 wherein the interrogation RF signal antenna has no previous stack information, and wherein for each respective gaming chip of the plurality of gaming chips, the respective instructions, when executed by the at least one processor, cause the at least one processor to generate the respective current stack information based on the respective chip information of the respective gaming chip, and to provide the respective current stack information to the respective second transponder of the respective gaming chip.

32. The RF gaming chip communication system of claim 31 wherein each of a plurality of next adjacent gaming chips sequentially receive the respective second RF signal from the preceding adjacent gaming chip, wherein the chip information of the receiving gaming chip is combined with the previous stack information received from the previous gaming chip to determine the current stack information.

33. The RF gaming chip communication system of claim 30 wherein for each respective gaming chip of the plurality of gaming chips, the respective instructions, when executed by the respective at least one processor, cause the respective at least one processor to, generate an RF acknowledgement signal in response to the second antenna and the second transceiver of the respective gaming chip in the first stack communicating the second RF signal, wherein respective the first antenna and the respective first transceiver of the respective gaming chip are further configured to communicate the RF acknowledgement signal to a different gaming chip in the first stack that communicated the first RF signal received by the respective gaming chip.

34. The RF gaming chip communication system of claim 30 wherein the first stack includes a last gaming chip and wherein the last gaming chip in the first stack, in response to not receiving an RF acknowledgement signal, transmits final stack information to at least the interrogator antenna.

35. The RF gaming chip communication system of claim 30 wherein a last gaming chip in the first stack, in response to not receiving an RF acknowledgement signal, transmits final stack information to at least a receiving antenna of a gaming table.

36. The RF gaming chip communication system of claim 30, wherein final stack information corresponds to a total monetary value of the gaming chips in the first stack, wherein the total monetary value is equal to a sum of the individual monetary values of each of the gaming chips in the first stack.

37. The RF gaming chip communication system of claim 30, further comprising:

a central processing system communicatively coupled to a plurality of the interrogator antenna and the interrogator transceivers,

wherein the central processing system receives a respective final stack information from the first stack and from at least a second stack of gaming chips.

38. The RF gaming chip communication system of claim 37 wherein the central processing system determines a total monetary value of the gaming chips in the first and the second stacks of gaming chips.

39. The RF gaming chip communication system of claim 37, further comprising:

a display communicatively coupled to the central processing system that is configured to display at least a total value of the gaming chips in each of the first and the second stacks of gaming chips.

40. The RF gaming chip communication system of claim 37 wherein the first and the second stacks of gaming chips reside in a first betting area such that each of the gaming chips in the first and the second stacks farthest from the interrogator antenna communicate their respective final stack values to the interrogator antenna and the interrogator transceiver so that the central processing system determines a total value of the gaming chips in the first betting area by summing the respective final stack values of each of the first and the second stacks of gaming chips.

41. The RF gaming chip communication system of claim 40 wherein the total value of the gaming chips for a betting table is determined by summing the total values of the gaming chips from all of a plurality of the betting areas on the betting table.

42. The RF gaming chip communication system of claim 30,

wherein each respective gaming chip includes a respective identifier stored in the processor-readable memory of the respective gaming chip that uniquely identifies the respective gaming chip, and wherein at least one respective identifier is included in the current stack information.

43. The RF gaming chip communication system of claim 42 wherein the second RF signal transmitted by each gaming chip includes the respective identifier of a current respective gaming chip such that a final chip information transmitted by a last gaming chip in the stack includes the identifiers of each of the gaming chips in the stack.

44. The RF gaming chip communication system of claim 30, further comprising:

a gaming chip tray;

a plurality of gaming chip stack-trays residing on the gaming chip tray; and

a plurality of tray interrogator antenna and tray interrogator transceivers, one tray interrogator antenna and tray interrogator transceiver in each one of the plurality of gaming chip stack-trays, wherein each of the tray interrogator antenna and tray interrogator transceivers is configured to initially transmit the interrogation RF signal to the plurality of gaming chips that are arranged in the stack and reside in the respective gaming chip stack-tray, and wherein the gaming chip in the stack closest to the tray interrogator antenna is responsive to the interrogation RF signal, and wherein the remaining gaming chips in the stack are not responsive to the interrogation RF signal.

45. A method for communicating information with gaming chips, the method comprising:

transmitting a first radio frequency (RF) signal to a stack of gaming chips having a bottom gaming chip and at least a second gaming chip adjacent to the bottom gaming chip, and wherein the bottom gaming chip is responsive to the first RF signal and the second gaming chip is not responsive to the first RF signal;

including at least a portion of chip information of the bottom gaming chip in stack information carried in a second RF signal;

transmitting the second RF signal from the bottom gaming chip to the second gaming chip after the bottom gaming chip is responsive to the first RF signal;

combining at least a portion of chip information of the second gaming chip with the portion of chip information of the bottom gaming chip;

including at least a portion of the combined chip information of the bottom gaming chip and the second gaming chip in stack information carried in a third RF signal; and

transmitting the third RF signal from the second gaming chip in response to the second RF signal, and wherein the bottom gaming chip is not responsive to the third RF signal.

46. The method of claim 45 wherein combining at least a portion of chip information of the second gaming chip with the portion of chip information of the bottom gaming chip includes determining, at the second gaming chip, a current value of the stack of gaming chips.

47. The method of claim 45, further comprising:

transmitting an RF acknowledgement signal from the second gaming chip in response to transmitting the third RF signal; and

receiving the RF acknowledgement signal by the bottom gaming chip, wherein the bottom gaming chip is not responsive to a subsequent RF signal.

48. The method of claim 45, further comprising:

transmitting a first RF acknowledgement signal from the second gaming chip in response to transmitting the third RF signal;

timing a period of time; and

communicating a final RF signal comprising the combined chip information of the bottom gaming chip and the second gaming chip in response to the second gaming chip not receiving a second RF acknowledgement signal from another adjacent gaming chip within the period of time.

49. A method for determining a total value of a plurality of gaming chips in a stack having a bottom and a top, each gaming chip comprising at least a first antenna and a second antenna, the method comprising:

communicating a first radio frequency (RF) signal from an interrogation antenna, wherein the first antenna of a first gaming chip at the bottom of the stack is responsive to the first RF signal and wherein the remaining gaming chips in the stack are not responsive to the first RF signal;

communicating a second RF signal from the second antenna of the first gaming chip, wherein the second RF signal comprises at least chip information stored in a processor-readable memory of the first gaming chip, and wherein the first antenna of an adjacent gaming chip in the stack is responsive to the second RF signal;

adding chip information of the adjacent gaming chip to the chip information of the first gaming chip carried by the second RF signal to determine stack information;

communicating the stack information from the second antenna of the adjacent gaming chip to the first antenna of a next adjacent gaming chip in the stack;

communicating an acknowledgement signal from the first antenna of the adjacent gaming chip in the stack to the first gaming chip;

sequentially repeating from a current respective gaming chip in the stack to a next to the top of the stack gaming chip,

adding chip information of the current respective gaming chip to the chip information of preceding gaming chips to determine current stack information;

communicating the current stack information from the second antenna of the current respective gaming chip to the first antenna of the next adjacent gaming chip in the stack; and

communicating the acknowledgement signal from the first antenna of the current respective gaming chip in the stack to a preceding gaming chip; and

communicating final stack information from a topmost gaming chip at the top of the stack, wherein the final stack information, and wherein the final stack information corresponds to the current stack information determined by the top most gaming chip.

50. The method of claim 49 wherein communicating the final stack information comprised communicating final stack information to the interrogation antenna.

51. The method of claim 49 wherein communicating the final stack information comprised communicating final stack information to a table antenna.

52. The method of claim 49 wherein transmitting the final stack information from the topmost gaming chip in the stack occurs in response to the topmost gaming chip in the stack not receiving the acknowledgement signal.

53. The method of claim 49 wherein the chip information of a respective gaming chip corresponds to a monetary value associated with the respective gaming chip, wherein the current stack information corresponds to the monetary value of the current gaming chip added to the monetary value of preceding gaming chips, and wherein the final stack information transmitted by the last gaming chip corresponds to a total monetary value for the stack of gaming chips.

54. The method of claim 53, further comprising:

communicating the final stack information transmitted by the top most gaming chip to a central processing system; and

associating the final stack information with a total value for the stack of gaming chips.

55. The method of claim 54, further comprising:

communicating a second final stack information transmitted by a second topmost gaming chip in a second stack of gaming chips to the central processing system, wherein the first and second stacks of gaming chips reside in a common betting area; and

associating the first final stack information and the second final stack information with the total value for the gaming chips residing in the common betting area.

56. The method of claim 49 wherein the chip information of a respective gaming chip corresponds to a respective identifier associated with the respective gaming chip, wherein the current stack information corresponds to the respective identifier of the current gaming chip combined to the respective identifiers of preceding gaming chips, and wherein the final stack information transmitted by the topmost gaming chip corresponds to all of the identifiers of the stack of gaming chips.