Light-emitting diode, method for making light-emitting diode, integrated light-emitting diode and method for making integrated light-emitting diode, method for growing a nitride-based III-V group compound semiconductor, light source cell unit, light-emitting diode

• US 7,754,504 B2
• Filed: 05/16/2006
• Issued: 07/13/2010
• Est. Priority Date: 05/16/2005
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yasuda, Atsushi, Tange, Takashi, Maeda, Yuki, Yanashima, Katsunori, Shiomi, Michinori, Miyajima, Takao, Ohmae, Akira, Ami, Takaaki, Tomiya, Shigetaka
• Primary Examiner(s): Gurley; Lynne A
• Assistant Examiner(s): Li; Meiya
• Application Number:
  US11/383,526
• Publication Number:
  US 20060258027A1
• Time in Patent Office: 1,519 Days
• Field of Search: 257/88, 257/89, 257/99, 257/E21.121, 257/E21.126, 257/E21.127, 257/E21.131, 257/E21.132, 257/E33.025, 438/22, 438/34, 438/36, 438/37, 438 45- 47, 438/478, 327 39- 41, 327/43.01, 327/44.011, 327/46.016, 327/49.01
• US Class Current: 438/22
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.

Claims

1. A method for making a light-emitting diode, comprising the steps of:

providing a substrate having a plurality of recessed portions on one main surface, each of the recessed portions having a floor and sidewalls;

growing a first nitride-based III-V group compound semiconductor layer (1) initially only from the floors of the recessed portions without using a mask so that the first nitride-based III-V group compound semiconductor initially exhibits a triangle in section in each recessed portion and having the floors of the recessed portions as bases, (2) thereafter continuing to grow the first nitride-based III-V group compound semiconductor until it r buries the recessed portion, (3) thereafter continuing to grow the first nitride-based III-V group compound semiconductor under such conditions that lateral growth is predominant until the first nitride-based III-V group semiconductor from adjacent recessed portions mutually contact each other, and (4) continuing to grow the first nitride-based III-V group compound semiconductor at least until it forms a first nitride-based III-V group layer with a planar surface;

growing a second nitride-based III-V group compound semiconductor layer on the first nitride-based III-V group compound semiconductor layer; and

successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.

2. The method according to claim 1, wherein in the course of the growth of the first nitride-based III-V group compound semiconductor layer, a dislocation occurs at an interface with the floor of each recessed portion and extends in a vertical direction relative to the main surface and bends in a direction parallel to the main surface at, or in the vicinity of, an inclined face of the triangle formed by the first nitride-based III-V group compound semiconductor layer.

3. The method according to claim 1, wherein when the first nitride-based III-V group compound semiconductor layer and the second nitride-based III-V group compound semiconductor layer are, respectively, grown, a first pit having a first width is formed in the substrate at the floor of each recessed portion and a second pit having a second width larger than the first width is formed in the substrate at opposite sides of each recessed portion.

4. The method according to claim 1, wherein each recessed portion has an inverted trapezoid shape in section.

5. The method according to claim 4, wherein when a depth of each recessed portion is taken as d, a width of the floor of each recessed portion is taken as W_g, and an angle established between an inclined face of the first nitride-based III-V group compound semiconductor layer in a state of a triangle in section and the one main surface of the substrate is taken as α

, d, W_g and α

are so determined as to establish the relation of 2d≧

W_g tan α

.

6. The method according to claim 1, wherein the plural recessed portions extend in first and second directions which mutually intersect each other.

7. The method according to claim 1, wherein,

the substrate and the first nitride-based III-V group compound semiconductor layer grown on the substrate are made of different materials, and

the recessed portions are formed in the first nitride-based III-V group semiconductor layer.

8. The method according to claim 1, wherein the substrate has an amorphous layer at opposite sides of each of the recessed portions.

9. The method according to claim 8, comprising the further step of subjecting a surface layer of the substrate to ion implantation and amorphousizing the surface layer to form the amorphous layer.

10. The method according to claim 8, wherein the amorphous layer is made of an insulating film formed on the substrate.

11. The method according to claim 1, wherein a first amorphous layer, a second amorphous layer and a third amorphous layer are successively formed on the substrate at opposite sides of each of the recessed portions, and the second amorphous layer enables the first amorphous layer and the third amorphous layer to be selectively etched.

12. The method according to claim 1, wherein after the lateral growth of the second nitride-based III-V group compound semiconductor layer, portions of the second nitride-based III-V group compound semiconductor layer other than those above the recessed portions are removed, the third nitride-based III-V group compound semiconductor layer is laterally grown on the second nitride-based III-V group compound semiconductor layer left over the recessed portions, and the active layer and the fourth nitride-based III-V group compound semiconductor layer are successively grown on the third nitride-based III-V group compound semiconductor layer.

13. The method according to claim 1, wherein after the lateral growth of the second nitride-based III-V group compound semiconductor layer, portions of the second nitride-based III-V group compound semiconductor layer other than those above the recessed portions are removed, a fifth nitride-based III-V group compound semiconductor layer is laterally grown on the second nitride-based III-V group compound semiconductor layer left over the recessed portions, and the third nitride-based III-V group compound semiconductor layer, the active layer and the fourth nitride-based III-V group compound semiconductor layer are successively grown on the fifth nitride-based III-V group compound semiconductor layer.