Method of removing the growth substrate of a semiconductor light emitting device

• US 7,754,507 B2
• Filed: 06/09/2005
• Issued: 07/13/2010
• Est. Priority Date: 06/09/2005
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Philips Lumileds Lighting Company LLC (Apollo Global Management, Inc.), Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Zhou, Ling, Shchekin, Oleg B., Epler, John E., Wall, Franklin J. Jr., Wierer, Jonathan J. Jr.
• Primary Examiner(s): Tran; Mihn-Loan T.
• Assistant Examiner(s): Sandvik; Benjamin P
• Application Number:
  US11/149,679
• Publication Number:
  US 20060281203A1
• Time in Patent Office: 1,860 Days
• Field of Search: 257/93, 257/95, 257/99, 438/26, 438/27, 438/28
• US Class Current: 438/26
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body

Abstract

A semiconductor structure formed on a growth substrate and including a light emitting layer disposed between an n-type region and a p-type region is attached to a carrier by a connection that supports the semiconductor structure sufficiently to permit removal of the growth substrate. In some embodiments, the semiconductor structure is a flip chip device. The semiconductor structure may be attached to the carrier by, for example, a metal bond that supports almost the entire lateral extent of the semiconductor structure, or by interconnects such as solder or gold stud bumps. An underfill material which supports the semiconductor structure is introduced in any spaces between the interconnects. The underfill material may be a liquid that is cured to form a rigid structure. The growth substrate may then be removed without causing damage to the semiconductor structure.

Claims

1. A method comprising:

providing a semiconductor structure grown on a growth substrate, the semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region, wherein a plurality of vias are etched through the p-type region and light emitting layer to expose portions of the n-type region, a plurality of metal n-contacts are disposed in the plurality of vias, and a metal p-contact is disposed on at least a portion of the p-type region disposed between two of the plurality of vias;

attaching the semiconductor structure to a carrier by at least one interconnect;

introducing an underfill in a cavity between the semiconductor structure and the carrier, wherein the underfill provides a rigid support for the semiconductor structure; and

removing the growth substrate;

wherein the underfill provides a rigid support for the semiconductor structure during removal of the growth substrate.

2. The method of claim 1 wherein introducing an underfill comprises:

disposing a liquid underfill material between the carrier and the semiconductor structure; and

curing the liquid underfill material to form a rigid support for the semiconductor structure.

3. The method of claim 1 wherein introducing an underfill comprises:

forming a rigid underfill layer on one of the semiconductor structure and the carrier prior to attaching; and

forming at least one opening in the rigid underfill layer for the at least one interconnect.

4. The method of claim 1 wherein the at least one interconnect connects a metal layer formed on the carrier to one of an n-contact and the p-contact.

5. The method of claim 1 wherein:

the at least one interconnect is coupled to a bottom surface of the semiconductor structure; and

a top surface of the semiconductor structure is less than 50 microns from a top surface of the carrier.

6. The method of claim 1 wherein the underfill comprises an organic material.

7. The method of claim 1 wherein the underfill comprises an inorganic material.

8. The method of claim 1 wherein the underfill comprises epoxy.

9. The method of claim 1 wherein the underfill comprises silicone.

10. The method of claim 9 further comprising particles of inorganic material disposed in the silicone.

11. The method of claim 1 wherein:

the at least one interconnect comprises gold; and

attaching comprises attaching by ultrasonic welding.

12. The method of claim 1 wherein the at least one interconnect comprises solder.

13. The method of claim 1 wherein a coefficient of thermal expansion of one of the at least one interconnect and the underfill is no more than twice a coefficient of thermal expansion of the other of the at least one interconnect and the underfill.

14. The method of claim 1 wherein:

the semiconductor structure is a III-nitride structure and the growth substrate is sapphire; and

removing comprises removing by laser dissociation.

15. The method of claim 14 wherein removing by laser dissociation comprises scanning a surface of the growth substrate with a laser.

16. The method of claim 1 wherein removing comprises removing by etching.

17. The method of claim 1 further comprising thinning the semiconductor structure after removing the growth substrate.

18. The method of claim 17 wherein thinning comprises etching to an etch stop layer disposed within the semiconductor structure.

19. The method of claim 1 further comprising roughening a surface of the semiconductor structure exposed by removing the growth substrate.

20. The method of claim 1 wherein the growth substrate is sapphire and the underfill provides a rigid support for the semiconductor structure during laser dissociation of the sapphire growth substrate.